Wear leveling mechanism using a DRAM buffer
View Patent ↗A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.
1. A memory system, comprising:
a controller configured to regulate read and write access to dynamic random access memory (DRAM) and one or more FLASH memory devices employed for random access memory applications;
a DRAM buffer component configured to provide temporary storage for data stored in the one or more FLASH memory devices wherein a size of the DRAM buffer component is adjusted based on data requirements of the random access memory application;
an eviction component configured to evict the data stored in the one or more FLASH memory devices to the DRAM buffer component in response to a replacement algorithm based on a write activity log; and
a wear leveling component that remaps data from heavily used areas of the one or more FLASH memory devices to lightly used areas using the DRAM buffer component to provide sector swapping, wherein the DRAM buffer component is not visible to a main memory.
2. The system of claim 1 , the DRAM buffer component is a dynamic random access memory component that is not visible to a standard operating system.
3. The system of claim 1 , the DRAM buffer component is provided as part of a dual inline memory module package.
4. The system of claim 1 , the FLASH memory devices are provided as part of a dual inline memory module package.
5. The system of claim 1 , the controller is provided as an application specific integrated circuit that occupies an expansion memory slot of a computer, the controller operates a wear leveling component to even data storage across the FLASH memory devices.
6. The system of claim 1 , data from the FLASH memory devices is moved to the buffer component during background operations of a computer.
7. The system of claim 6 , further comprising a counter that is monitored to determine wear of a selected address location.
8. The system of claim 1 , further comprising an operating system component that provides a free list of available sectors in the FLASH memory devices or the buffer component, where the free list is employed to re-map memory locations within the FLASH memory devices.
9. The system of claim 1 , further comprising an expansion slot adapted with dual inline memory modules for additional buffer capacity.
10. The system of claim 1 , further comprising an expansion slot adapted with dual inline memory modules for additional FLASH memory capacity.
11. The system of claim 1 , further comprising an address and data bus having at least two channels, where wear leveling is performed in accordance with at least one of the channels.
12. The system of claim 11 , further comprising at least one channel configured as a DRAM channel.
13. The system of claim 11 , further comprising at least one channel configured as a FLASH memory channel.
14. The system of claim 1 , further comprising a victim page handling component.
15. The system of claim 14 , wherein the eviction component and the victim page handling component facilitate wear leveling.
16. The system of claim 14 , further comprising a sector data merge control component to facilitate wear leveling.
17. A method to to operate a memory subsystem, comprising:
remapping one or more FLASH memory devices employed for random access memory applications; and
storing data temporarily in a buffer component during the remapping of the one or more FLASH memory devices, wherein the buffer component is not visible to a main supersystem;
evicting data stored in the one or more FLASH memory devices to the buffer component in response to a replacement algorithm based on a write activity log; and
resizing the buffer component by a controller based on data requirements of the random access memory applications.
18. The method of claim 17 , further comprising employing a FLASH memory device leveling component to swap data locations within the one or more FLASH memory devices.
19. A memory system, comprising:
means for controlling write access to a DRAM and FLASH memory devices;
means for temporarily storing data from the FLASH memory devices in a DRAM memory device, wherein the DRAM memory device is not visible to the FLASH memory devices and wherein a size of the DRAM memory device is adjustable based on an amount of data to be written in the write access;
means for evicting data stored in the one or more FLASH memory devices to a buffer component in response to a replacement algorithm based on a write activity log; and
means for remapping data in the FLASH memory devices.