Patent Assignment
Reel/Frame 036051/0786
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-07-02
Received: 2015-07-02
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(51)
METHOD AND SYSTEM FOR PROVIDING CONTACT TO A FIRST POLYSILICON LAYER IN A FLASH MEMORY DEVICE
App. No. 13/566,741
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METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER
App. No. 13/428,848
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SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/323,370
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PLL
App. No. 13/310,069
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 13/253,634
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SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 13/195,722
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SIH4 SOAK FOR LOW HYDROGEN SIN DEPOSITION TO IMPROVE FLASH MEMORY DEVICE PERFORMANCE
App. No. 13/165,522
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METHOD TO SEPERATE STORAGE REGIONS IN THE MIRROR BIT DEVICE
App. No. 13/156,122
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SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 13/155,278
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SACRIFICIAL NITRIDE AND GATE REPLACEMENT
App. No. 13/153,558
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SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
App. No. 13/094,744
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HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
App. No. 13/069,710
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SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
App. No. 13/069,269
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SEMICONDUCTOR DEVICE WITH VOID DETECTION MONITOR
App. No. 13/043,383
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A/D CONVERTER
App. No. 13/036,429
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SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
App. No. 13/026,075
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
App. No. 13/024,979
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SEMICONDUCTOR MEMORY
App. No. 13/020,636
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SYSTEM AND METHOD FOR ADDRESSING THRESHOLD VOLTAGE SHIFTS OF MEMORY CELLS IN AN ELECTRONIC PRODUCT
App. No. 13/011,706
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LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
App. No. 12/970,687
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PRECISION TRENCH FORMATION THROUGH OXIDE REGION FORMATION FOR A SEMICONDUCTOR DEVICE
App. No. 12/961,352
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DUAL SPACER FORMATION IN FLASH MEMORY
App. No. 12/960,437
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FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/912,602
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BOOSTER CIRCUIT AND SEMICONDUCTOR MEMORY
App. No. 12/892,251
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STITCH BUMP STACKING DESIGN FOR OVERALL PACKAGE SIZE REDUCTION FOR MULTIPLE STACK
App. No. 12/853,856
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SEMICONDUCTOR MEMORY, SYSTEM, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY
App. No. 12/850,470
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ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES
App. No. 12/844,392
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POWER SUPPLY DEVICE, CONTROL CIRCUIT AND METHOD FOR CONTROLLING POWER SUPPLY DEVICE
App. No. 12/762,668
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METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
App. No. 12/720,547
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POWER SUPPLY AND POWER CONTROL DEVICE
App. No. 12/716,133
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FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES
App. No. 12/690,590
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MEMORY DEVICE
App. No. 12/683,732
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VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
App. No. 12/646,291
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POWER SUPPLY APPARATUS AND POWER SUPPLY METHOD
App. No. 12/636,764
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DC/DC CONVERTER CONTROL CIRCUIT AND DC/DC CONVERTER CONTROL METHOD
App. No. 12/479,014
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IMPROVEMENT IN CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY
App. No. 12/473,037
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TRANSMITTING/RECEIVING SYSTEM, NODE AND COMMUNICATION METHOD
App. No. 12/410,086
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RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD
App. No. 12/337,963
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SEMICONDUCTOR INTEGRATED CIRCUIT IN A CARRY COMPUTATION NETWORK HAVING A LOGIC BLOCKS WHICH ARE DYNAMICALLY RECONFIGURABLE
App. No. 12/332,673
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MOVING PROGRAM VERIFY LEVEL FOR PROGRAMMING OF MEMORY
App. No. 12/326,388
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MANUFACTURING STACKED SEMICONDUCTOR DEVICE
App. No. 12/210,113
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COMMAND CONTROL FOR SYNCHRONOUS MEMORY DEVICE
App. No. 12/138,307
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INSTANT HARDWARE ERASE FOR CONTENT RESET AND PSEUDO-RANDOM NUMBER GENERATION
App. No. 12/129,737
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USING LPDDR1 BUS AS TRANSPORT LAYER TO COMMUNICATE TO FLASH
App. No. 12/048,474
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PARTIAL ALLOCATE PAGING MECHANISM USING A CONTROLLER AND A BUFFER
App. No. 12/026,302
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WEAR LEVELING MECHANISM USING A DRAM BUFFER
App. No. 12/026,299
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SEMICONDUCTOR DEVICE HAVING MULTIPLE STORAGE REGIONS
App. No. 12/005,869
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FLASH MEMORY CELL WITH A FLAIR GATE
App. No. 11/801,823
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SECURE CO-PROCESSING MEMORY CONTROLLER INTEGRATED INTO AN EMBEDDED MEMORY SUBSYSTEM
App. No. 11/614,309
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RECONFIGURABLE CIRCUIT
App. No. 11/545,477
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Flash memory programming with data dependent control of source lines
App. No. 11/229,529
→