IP Library Granted Patent US 8,309,455
Granted Patent B2
US 8,309,455 · App. 13/165,522 · Granted Nov 13, 2012

SiH

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,309,455
App. No.
13/165,522
Granted
Nov 13, 2012
Kind
B2
Abstract

Prior to deposition of a silicon nitride (SiN) layer on a structure, a non-plasma enhanced operation is undertaken wherein the structure is exposed to silane (SiH 4 ) flow, reducing the overall exposure of the structure to hydrogen radicals. This results in the silicon nitride being strongly bonded to the structure and in improved performance.

Claims (16)

1. A method of fabricating an electronic structure comprising:

forming at least one copper containing body;

performing a plasma treatment on the electronic structure to remove copper oxide layers from the at least one copper containing body;

performing a non-plasma treatment on the electronic structure to form copper silicide layers on the at least one copper containing body;

performing a plasma-enhanced deposition to deposit a silicon nitride layer on the electronic structure to contact the copper silicide layers.

2. The method of claim 1 , wherein performing a non-plasma treatment comprises exposing the electronic structure to a silicon-containing entity.

3. The method of claim 2 , wherein performing a non-plasma treatment comprises exposing the electronic structure to silane.

4. The method of claim 1 , wherein a first copper containing body is in electrical connection with a control gate of a transistor.

5. The method of claim 1 , wherein a second copper containing body is in electrical connection with a source of a transistor, and wherein a third copper containing body is in electrical connection with a drain of the transistor.

6. The method of claim 1 , wherein performing a plasma-enhanced deposition comprises exposing the electronic structure to silane and ammonia.

7. The method of claim 1 , wherein performing a plasma treatment on the electronic structure comprises exposing the electronic structure to ammonia at 100-1000 sccm, at a temperature of 300-500 degrees centigrade, at an RF power of 10-3000 watts, and at a pressure of 0.1-100 Torr, and wherein the plasma treatment is performed for 0.1-60 seconds.

8. The method of claim 7 , wherein performing a plasma treatment on the electronic structure comprises exposing the electronic structure to ammonia at 160 sccm, at a temperature of 400 degrees centigrade, at an RF power of 300 watts, and at a pressure of 4.2 Torr, and wherein the plasma treatment is performed for 10 seconds.

9. The method of claim 1 , wherein performing a non-plasma treatment on the electronic structure comprises exposing the electronic structure to silane at 10-1000 sccm, at a temperature of 300-500 degrees centigrade, and at a pressure of 0.1-100 Torr for 0.1-10 seconds.

10. The method of claim 9 , wherein performing a non-plasma treatment on the electronic structure comprises exposing the electronic structure to silane at 322 sccm, at a temperature of 400 degrees centigrade, and a pressure of 4.2 Torr for 1 second.

11. The method of claim 1 , wherein performing a plasma-enhanced deposition on the electronic structure comprises exposing the electronic structure to silane at 250-350 sccm, ammonia at 100-1000 sccm, and nitrogen at 10,000-30,000 sccm, at 300-500 degrees centigrade, at an RF power of 10-3000 watts, and at a pressure of 0.1-100 Torr.

12. The method of claim 11 , wherein performing a plasma-enhanced deposition on the electronic structure comprises exposing the electronic structure to silane at 250-350 sccm, ammonia at 320 sccm, and nitrogen at 22000 sccm, at 400 degrees centigrade, at an RF power of 830 watts, and at a pressure of 4.2 Torr.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 044094/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 044051/0244 →
RELEASE OF SECURITY INTEREST Recorded Sep 28, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 044052/0280 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0786 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →