Methods for forming a memory cell having a top oxide spacer
View Patent ↗Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
1. A memory cell comprising:
a source/drain region formed in a substrate between trenches;
a first oxide layer formed above said source/drain region and in said trenches;
a charge storage layer formed above said first oxide layer wherein a space is formed between said charge storage layer and a charge storage layer of an adjacent memory cell in said trenches;
an insulation film layer formed in said trenches to fill said space between said charge storage layer and said charge storage layer of said adjacent memory cell, wherein said insulation film layer is formed to rise a predetermined distance above said space; and
a second oxide layer formed above said charge storage layer; and
a polysilicon layer formed above said oxide layer.
2. The memory cell of claim 1 wherein said insulation film layer formed in said trenches is bounded on both sides by said charge storage layer.
3. The memory cell of claim 1 wherein said insulation film layer is formed
from material selected from the group that includes ALD, HARP, eHARP, HTO, TEOS, HDP, BPSG, SOG and un-doped poly.
4. The memory cell of claim 1 wherein said charge storage layer is formed
from SiRN.
5. The memory cell of claim 1 wherein said second oxide layer is formed above said insulation film layer and along sidewalls of said trenches.
6. The memory cell of claim 1 wherein said polysilicon layer extends a predetermined distance into said trenches.
7. The memory cell of claim 1 wherein said trenches comprise STI trenches.
8. A memory cell array comprising:
input and output circuitry; and
a plurality of memory cells comprising:
a source/drain region formed in a substrate between trenches;
a first oxide layer formed above said source/drain region and in said trenches;
a charge storage layer formed above said oxide layer wherein a space is formed between said charge storage layer and a charge storage layer of an adjacent memory cell in said trenches;
an insulation film layer formed in said trenches to fill said space between said separated portions of said charge storage layer, wherein said insulation film layer is formed to rise a predetermined distance above said space; and
a second oxide layer formed above said charge storage layer; and
a polysilicon layer formed above said oxide layer.
9. The memory cell of claim 8 wherein said insulation film layer formed in said trenches is bounded on both sides by said charge storage layer.
10. The memory cell of claim 8 wherein said insulation film layer is formed from material selected from the group that includes ALD, HARP, eHARP, HTO, TEOS, HDP, BPSG, SOG and un-doped poly.
11. The memory cell of claim 8 wherein said charge storage layer is formed from SiRN.
12. The memory cell of claim 8 wherein said second oxide layer is formed above said insulation film layer and along sidewalls of said trenches.
13. The memory cell of claim 8 wherein said polysilicon layer extends a predetermined distance into said trenches.