Semiconductor device and control method therefor
View Patent ↗A semiconductor device includes an insulation layer ( 14 ) provided on a semiconductor substrate ( 12 ), a p-type semiconductor region ( 16 ) provided on the insulation layer, an isolation region ( 18 ) provided that surrounds the p-type semiconductor region to reach the insulation layer, an n-type source region ( 20 ) and an n-type drain region ( 22 ) provided on the p-type semiconductor region, a charge storage region ( 30 ) provided above the p-type semiconductor region between the n-type source region and the n-type drain region, and an voltage applying portion that applies a different voltage to the p-type semiconductor region while any of programming, erasing and reading a different data of a memory cell that has the charge storage region is being preformed.
1. A method of controlling a semiconductor device having an insulation layer provided on a semiconductor substrate; a p-type semiconductor region provided on the insulation layer; an isolation region provided that surrounds the p-type semiconductor region to reach the insulation layer; an n-type source region and an n-type drain region provided on the p-type semiconductor region; a charge storage region provided above the p-type semiconductor region between the n-type source region and the n-type drain region, the method of controlling the semiconductor device comprising the steps of:
applying a first voltage to the p-type semiconductor region to write a charge into the charge storage region while any of programming, erasing, and reading of a memory cell having the charge storage region is being performed;
applying a second voltage, different from the first voltage, to the p-type semiconductor region to write a charge into the charge storage region while said any of programming, erasing, and reading of the memory cell is being performed;
applying a third voltage to the p-type semiconductor region to erase the charge from the charge storage region; and
applying a fourth voltage, lower than the third voltage, to the p-type semiconductor region to erase the charge from the charge storage region.
2. The method as claimed in claim 1 , wherein a difference between the first voltage and the third voltage is substantially identical to that between the second voltage and the fourth voltage.
3. The method as claimed in claim 2 , wherein the fourth voltage is between the first voltage and the third voltage.
4. The method as claimed in claim 1 further comprising a step of applying a fifth voltage to the p-type semiconductor region to read a charge state in the charge storage region.
5. The method as claimed in claim 4 , wherein the fifth voltage is substantially identical to the first voltage.
6. The method as claimed in claim 1 ,
wherein the step of applying the first voltage includes a step of applying the first voltage in a first period while a charge is being written into the charge storage region; and
wherein the step of applying the second voltage includes a step of applying the second voltage, higher than the first voltage, in a second period while the charge is being written into the charge storage region after the first period.
7. The method as claimed in claim 1 ,
wherein the step of applying the first voltage includes a step of applying the first voltage in a first period while a charge is being erased from the charge storage region; and
wherein the step of applying the second voltage includes a step of applying the second voltage, lower than the first voltage, in a second period while the charge is being erased from the charge storage region after the first period.
8. The method as claimed in claim 1 ,
wherein the memory cell is a reference cell;
wherein the step of applying the first voltage includes a step of reading data from the reference cell; and
wherein the step of applying the second voltage includes a step of reading the data from the reference cell.
9. A method of controlling a semiconductor device having an insulation layer provided on a semiconductor substrate; a p-type semiconductor region provided on the insulation layer; an isolation region provided that surrounds the p-type semiconductor region to reach the insulation layer and that includes an oxide silicon region and an n-type semiconductor region; an n-type source region and an n-type drain region provided on the p-type semiconductor region; a charge storage region provided above the p-type semiconductor region between the n-type source region and the n-type drain region, the method of controlling the semiconductor device comprising the steps of:
applying a first voltage to the p-type semiconductor region to write a charge into the charge storage region while any of programming, erasing, and reading of a memory cell having the charge storage region is being performed; and
applying a second voltage, different from the first voltage, to the p-type semiconductor region to write a charge into the charge storage region while said any of programming, erasing, and reading of the memory cell is being performed;
applying a third voltage to the p-type semiconductor region to erase the charge from the charge storage region; and
applying a fourth voltage, lower than the third voltage, to the p-type semiconductor region to erase the charge from the charge storage region.
10. The method as claimed in claim 9 , wherein a difference between the first voltage and the third voltage is substantially identical to that between the second voltage and the fourth voltage.
11. The method as claimed in claim 10 , wherein the fourth voltage is between the first voltage and the third voltage.
12. The method as claimed in claim 9 further comprising a step of applying a fifth voltage to the p-type semiconductor region to read a charge state in the charge storage region.
13. The method as claimed in claim 12 , wherein the fifth voltage is substantially identical to the first voltage.
14. The method as claimed in claim 9 ,
wherein the step of applying the first voltage includes a step of applying the first voltage in a first period while a charge is being written into the charge storage region; and
wherein the step of applying the second voltage includes a step of applying the second voltage, higher than the first voltage, in a second period while the charge is being written into the charge storage region after the first period.
15. The method as claimed in claim 9 ,
wherein the step of applying the first voltage includes a step of applying the first voltage in a first period while a charge is being erased from the charge storage region; and
wherein the step of applying the second voltage includes a step of applying the second voltage, lower than the first voltage, in a second period while the charge is being erased from the charge storage region after the first period.
16. The method as claimed in claim 9 ,
wherein the memory cell is a reference cell;
wherein the step of applying the first voltage includes a step of reading data from the reference cell; and
wherein the step of applying the second voltage includes a step of reading the data from the reference cell.