Patent Assignment
Reel/Frame 028837/0076
SECURITY AGREEMENT
Recorded: 2012-08-23
Received: 2012-08-23
Pages: 174
Assignors
SPANSION INC.
Executed: 2010-05-10
SPANSION LLC
Executed: 2010-05-10
SPANSION TECHNOLOGY INC.
Executed: 2010-05-10
SPANSION TECHNOLOGY LLC
Executed: 2010-05-10
Assignee
BARCLAYS BANK PLC
745 SEVENTH AVENUE, NEW YORK, NY, 10019, UNITED STATES
Covered Applications
(100)
APPARATUS AND METHOD FOR ROUNDED ONO FORMATION IN A FLASH MEMORY DEVICE
App. No. 13/540,373
→
METHOD AND SYSTEM FOR PROVIDING CONTACT TO A FIRST POLYSILICON LAYER IN A FLASH MEMORY DEVICE
App. No. 13/465,649
→
MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD OF FABRICATING SAME
App. No. 13/357,252
→
METHOD AND DEVICE EMPLOYING POLYSILICON SCALING
App. No. 13/294,098
→
SONOS FLASH MEMORY DEVICE
App. No. 13/275,989
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 13/253,634
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
App. No. 13/206,380
→
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
App. No. 13/195,722
→
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
App. No. 13/165,689
→
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
App. No. 13/156,763
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/156,766
→
METHOD TO SEPERATE STORAGE REGIONS IN THE MIRROR BIT DEVICE
App. No. 13/156,122
→
DETERMINING A LOGIC STATE BASED ON CURRENTS RECEIVED BY A SENSE AMPLIFER
App. No. 13/154,616
→
SACRIFICIAL NITRIDE AND GATE REPLACEMENT
App. No. 13/153,558
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TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
App. No. 13/107,724
→
SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
App. No. 13/094,744
→
REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF
App. No. 13/123,698
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HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
App. No. 13/069,710
→
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF
App. No. 13/069,269
→
SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME
App. No. 13/052,865
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METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
App. No. 13/044,313
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SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREFOR
App. No. 13/026,075
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PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
App. No. 13/025,979
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SEMICONDUCTOR MANUFACTURING APPARATUS AND CONTROL SYSTEM AND CONTROL METHOD THEREFOR
App. No. 13/020,692
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/015,072
→
MEMORY WITH EXTENDED CHARGE TRAPPING LAYER
App. No. 12/982,006
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SYSTEM, METHOD AND APPARATUS FOR REDUCING PLASMA NOISE ON POWER PATH OF ELECTROSTATIC CHUCK
App. No. 12/979,654
→
EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING
App. No. 12/973,756
→
PROCESS MARGIN ENGINEERING IN CHARGE TRAPPING FIELD EFFECT TRANSISTORS
App. No. 12/973,631
→
SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING
App. No. 12/971,818
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LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
App. No. 12/970,687
→
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
App. No. 12/970,675
→
STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THROUGH AUTO GENERATION OF VIA FILL
App. No. 12/964,594
→
HIGH PERFORMANCE LOW PROFILE QFN/LGA
App. No. 12/964,523
→
FLIP-CHIP PACKAGE COVERED WITH TAPE
App. No. 12/962,479
→
WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE
App. No. 12/961,379
→
METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION
App. No. 12/960,411
→
DUAL SPACER FORMATION IN FLASH MEMORY
App. No. 12/960,437
→
MEMORY DEVICE PERIPHERAL INTERCONNECTS
App. No. 12/943,679
→
FLASH MEMORY DEVICE WITH WORD LINES OF UNIFORM WIDTH AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/912,602
→
SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
App. No. 12/910,331
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/901,990
→
SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD
App. No. 12/900,370
→
Apparatus and method for read preamble disable
App. No. 12/879,992
→
APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE
App. No. 12/880,018
→
STRUCTURE, METHOD AND SYSTEM FOR ASSESSING BONDING OF ELECTRODES IN FCB PACKAGING
App. No. 12/877,661
→
STITCH BUMP STACKING DESIGN FOR OVERALL PACKAGE SIZE REDUCTION FOR MULTIPLE STACK
App. No. 12/853,856
→
REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF
App. No. 12/852,970
→
ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES
App. No. 12/844,392
→
BITLINE VOLTAGE DRIVER
App. No. 12/842,409
→
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE BY CONSIDERING THE EXTINCTION COEFFICIENT DURING ETCHING OF AN INTERLAYER INSULATING FILM
App. No. 12/840,063
→
METHOD AND SYSTEM FOR THIN MULTI CHIP STACK PACKAGE WITH FILM ON WIRE AND COPPER WIRE
App. No. 12/826,366
→
HIGH READ SPEED MEMORY WITH GATE ISOLATION
App. No. 12/824,352
→
METHOD AND STRUCTURE OF MINIMIZING MOLD BLEEDING ON A SUBSTRATE SURFACE OF A SEMICONDUCTOR PACKAGE
App. No. 12/818,866
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ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL
App. No. 12/792,129
→
STRAPPING CONTACT FOR CHARGE PROTECTION
App. No. 12/790,578
→
PARTIAL LOCAL SELF BOOSTING FOR NAND
App. No. 12/783,351
→
METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
App. No. 12/770,805
→
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
App. No. 12/729,905
→
SYSTEMS AND METHODS FOR CONTROLLING AN ELECTRONIC DEVICE
App. No. 12/723,582
→
HOME AND BUILDING AUTOMATION
App. No. 12/723,590
→
ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES
App. No. 12/723,589
→
NAND ARRAY SOURCE/DRAIN DOPING SCHEME
App. No. 12/722,014
→
NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
App. No. 12/722,083
→
METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
App. No. 12/720,547
→
APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY
App. No. 12/706,710
→
PLANAR CELL ONO CUT USING IN-SITU POLYMER DEPOSITION AND ETCH
App. No. 12/703,586
→
METHOD AND SYSTEM FOR AUTOMATED GENERATION OF MASKS FOR SPACER FORMATION FROM A DESIRED FINAL WAFER PATTERN
App. No. 12/701,391
→
SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY
App. No. 12/699,635
→
SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE
App. No. 12/697,707
→
METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS
App. No. 12/696,409
→
HIGH SPEED MEMORY HAVING A PROGRAMMABLE READ PREAMBLE
App. No. 12/691,633
→
FIELD UPGRADABLE FIRMWARE FOR ELECTRONIC DEVICES
App. No. 12/690,617
→
FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES
App. No. 12/690,590
→
MEMORY DEVICE
App. No. 12/683,732
→
LINE-EDGE ROUGHNESS IMPROVEMENT FOR SMALL PITCHES
App. No. 12/648,059
→
READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION
App. No. 12/646,279
→
SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK
App. No. 12/644,457
→
PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY
App. No. 12/575,137
→
VARIED SILICON RICHNESS SILICON NITRIDE FORMATION
App. No. 12/556,199
→
A NAND FLASH MEMORY DEVICE
App. No. 12/489,226
→
CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE
App. No. 12/473,081
→
IMPROVEMENT IN CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY
App. No. 12/473,037
→
RADIATION DETECTING DEVICE AND METHOD OF OPERATING
App. No. 12/468,615
→
DIRECT POINTER ACCESS AND XIP REDIRECTOR FOR EMULATION OF MEMORY-MAPPED DEVICES
App. No. 12/433,159
→
SONOS MEMORY CELLS HAVING NON-UNIFORM TUNNEL OXIDE AND METHODS FOR FABRICATING SAME
App. No. 12/432,441
→
ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT
App. No. 12/390,550
→
SYSTEMS AND METHODS FOR LOCATING ERROR BITS IN ENCODED DATA
App. No. 12/368,835
→
GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE
App. No. 12/368,023
→
FRACTURED ERASE SYSTEM AND METHOD
App. No. 12/366,519
→
Self-aligned double patterning for memory and other microelectronic devices
App. No. 12/322,105
→
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
App. No. 12/342,016
→
RADIATION-DETECTING STRUCTURES
App. No. 12/340,295
→
RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD
App. No. 12/337,963
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/337,134
→
MOVING PROGRAM VERIFY LEVEL FOR PROGRAMMING OF MEMORY
App. No. 12/326,388
→
ELECTROPLATING APPARATUS AND METHOD WITH UNIFORMITY IMPROVEMENT
App. No. 12/273,289
→
HIGH ULTRAVIOLET LIGHT ABSORBANCE SILICON OXYNITRIDE FILM FOR IMPROVED FLASH MEMORY DEVICE PERFORMANCE
App. No. 12/313,134
→
ERROR CORRECTION FOR FLASH MEMORY
App. No. 12/267,017
→
FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS
App. No. 12/266,512
→