Sacrificial nitride and gate replacement
Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.
1. A method of forming a memory device comprising memory cells and bit line openings therebetween, comprising:
forming charge storage layers on a semiconductor substrate, nitride layers on the charge storage layers, first poly layers on the charge storage layers, and bit line dielectrics in the bit line openings;
removing the first poly layers to expose at least portions of upper surfaces of the nitride layers; and
oxidizing the nitride layers to form top oxides.
2. The method of claim 1 further comprising forming a second poly layer or a word line over the top oxides.
3. The method of claim 1 , wherein forming charge storage layers comprises:
forming dielectric layers on the semiconductor substrate;
forming openings between the semiconductor substrate and the nitride layers by removing end portions of the dielectric layers; and
forming charge storage material layers in the openings.
4. The method of claim 3 , wherein the memory cell comprises two charge storage nodes that are separated from each other by the dielectric layers.
5. The method of claim 4 , wherein the two charge storage nodes comprise an ORPRO layer.
6. The method of claim 1 , wherein oxidizing the nitride layers comprises a slot plane antenna process.
7. The method of claim 1 , wherein the nitride layer comprises silicon nitrides.
8. A method of forming a memory device comprising memory cells and bit line openings therebetween, comprising:
forming charge storage layers on a semiconductor substrate, nitride layers on the charge storage layers, first poly layers on the charge storage layers, and bit line dielectrics in the bit line openings;
removing the first poly layers to expose at least portions of upper surfaces of the nitride layers;
oxidizing the nitride layers to form top oxides; and
forming a second poly layer over the top oxides.
9. The method of claim 8 , wherein forming charge storage layers comprises:
forming dielectric layers on the semiconductor substrate;
forming openings between the semiconductor substrate and the nitride layers by removing end portions of the dielectric layers; and
forming charge storage material layers in the openings.
10. The method of claim 9 , wherein the memory cell comprises two charge storage nodes that are separated from each other by the dielectric layers.
11. The method of claim 10 , wherein the two charge storage nodes comprise an ORPRO layer.
12. The method of claim 8 , wherein oxidizing the nitride layers comprises a slot plane antenna process.
13. The method of claim 8 , wherein the nitride layer comprises silicon nitrides.
14. A method of forming a memory device comprising memory cells and bit line openings therebetween, comprising:
forming charge storage layers on a semiconductor substrate, nitride layers on the charge storage layers, first poly layers on the charge storage layers, and bit line dielectrics in the bit line openings;
removing the first poly layers to expose at least portions of upper surfaces of the nitride layers;
oxidizing the nitride layers to form top oxides; and
forming a word line over the top oxides.
15. The method of claim 14 , wherein forming charge storage layers comprises:
forming dielectric layers on the semiconductor substrate;
forming openings between the semiconductor substrate and the nitride layers by removing end portions of the dielectric layers; and
forming charge storage material layers in the openings.
16. The method of claim 15 , wherein the memory cell comprises two charge storage nodes that are separated from each other by the dielectric layers.
17. The method of claim 16 , wherein the two charge storage nodes comprise an ORPRO layer.
18. The method of claim 15 , wherein the nitride layer comprises silicon nitrides.
19. The method of claim 14 , wherein oxidizing the nitride layers comprises a slot plane antenna process.
20. The method of claim 14 , wherein the nitride layer comprises silicon nitrides.