Stress reduction on vias and yield improvement in layout design through auto generation of via fill
View Patent ↗A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.
1. A process of automatic via doubling in a layout of a semiconductor device, comprising:
selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers;
selecting at least two metal layers of the at least one cell for via doubling;
selecting metal/metal intersection areas out of the at least two metal layers using a computer, wherein a metal/metal intersection area comprises an existing via interconnecting the at least two metal layers; and
dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout, and wherein a maximum number of additional vias are fitted into each of the selected metal/metal intersection areas without changing metal layer dimensions or layout routing.
2. The process for automatic via doubling of claim 1 , wherein portions of the at least one cell are excluded from the via doubling.
3. The process for automatic via doubling of claim 1 , further comprising a plurality of cells, wherein at least one cell of the plurality of cells is excluded from the via doubling, wherein all metal layers of the excluded cell are also excluded from the via doubling.
4. The process for automatic via doubling of claim 1 , wherein additional vias are added to a selected metal/metal intersection area while adhering to at least one of design rule check and layout versus schematic requirements.
5. The process for automatic via doubling of claim 1 , wherein additional vias are added to a selected metal/metal intersection area without increasing metal layer width and without requiring layout rerouting.
6. The process for automatic via doubling of claim 1 , wherein a cell comprises a plurality of transistor structures providing one of a Boolean logic function and a storage function.
7. The process for automatic via doubling of claim 1 , wherein the layout is contained in a database.
8. A non-transitory computer readable media comprising computer-executable instructions stored therein for automatic via doubling in a layout of a semiconductor device, the computer-executable instructions comprising:
instructions to select at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers;
instructions to select at least two metal layers of the at least one cell for via doubling;
instructions to select metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection area comprises an existing via interconnecting the at least two metal layers; and
instructions to dimensionally fit additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout, and wherein a maximum number of additional vias are fitted into each of the selected metal/metal intersection areas without changing metal layer dimensions or layout routing.
9. The non-transitory computer readable media of claim 8 , wherein portions of the at least one cell are excluded from the via doubling.
10. The non-transitory computer readable media of claim 8 , further comprising a plurality of cells, wherein at least one cell of the plurality of cells is excluded from the via doubling, wherein all metal layers of the excluded cell are also excluded from the via doubling.
11. The non-transitory computer readable media of claim 8 , wherein additional vias are added to a selected metal/metal intersection area while adhering to at least one of design rule check and layout versus schematic requirements.
12. The non-transitory computer readable media of claim 8 , wherein additional vias are added to a selected metal/metal intersection area without increasing metal layer width and without requiring layout rerouting.
13. The non-transitory computer readable media of claim 8 , wherein a cell comprises a plurality of transistor structures providing one of a Boolean logic function and a storage function.
14. The non-transitory computer readable media of claim 8 , wherein the layout is contained in a database.
15. An apparatus for automatic via doubling in a layout of a semiconductor device, comprising:
a means for selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers;
a means for selecting at least two metal layers of the at least one cell for via doubling;
a means for selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection area comprises an existing via interconnecting the at least two metal layers; and
a means for dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout, and wherein a maximum number of additional vias are fitted into each of the selected metal/metal intersection areas without changing metal layer dimensions or layout routing.
16. The apparatus of claim 15 , wherein portions of the at least one cell are excluded from the via doubling.
17. The apparatus of claim 15 , further comprising a plurality of cells, wherein at least one cell of the plurality of cells is excluded from the via doubling, wherein all metal layers of the excluded cell are also excluded from the via doubling.
18. The process for via fill generation of claim 15 , wherein additional vias are added to a selected metal/metal intersection area while adhering to at least one of design rule check and layout versus schematic requirements.
19. The process for via fill generation of claim 15 , wherein additional vias are added to a selected metal/metal intersection area without increasing metal layer width and without requiring layout rerouting.
20. The process for via fill generation of claim 15 , wherein a cell comprises a plurality of transistor structures providing one of a Boolean logic function and a storage function.
21. The process for via fill generation of claim 15 , wherein the layout is contained in a database.