Patent Assignment
Reel/Frame 036051/0256
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-07-02
Received: 2015-07-02
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(50)
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
App. No. 13/156,763
→
FABRICATION METHOD FOR SEMICONDUCTOR DEVICE HAVING LAMINATED ELECTRONIC CONDUCTOR ON BIT LINE
App. No. 13/081,777
→
PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
App. No. 13/025,979
→
SEMICONDUCTOR MEMORY DEVICE FEATURING SELECTIVE DATA STORAGE IN A STACKED MEMORY CELL STRUCTURE
App. No. 13/005,456
→
PROCESS MARGIN ENGINEERING IN CHARGE TRAPPING FIELD EFFECT TRANSISTORS
App. No. 12/973,631
→
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
App. No. 12/970,675
→
STRESS REDUCTION ON VIAS AND YIELD IMPROVEMENT IN LAYOUT DESIGN THROUGH AUTO GENERATION OF VIA FILL
App. No. 12/964,594
→
PLL CIRCUIT
App. No. 12/917,219
→
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
App. No. 12/901,990
→
STRUCTURE, METHOD AND SYSTEM FOR ASSESSING BONDING OF ELECTRODES IN FCB PACKAGING
App. No. 12/877,661
→
BITLINE VOLTAGE DRIVER
App. No. 12/842,409
→
HIGH READ SPEED MEMORY WITH GATE ISOLATION
App. No. 12/824,352
→
METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
App. No. 12/770,805
→
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
App. No. 12/729,905
→
ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES
App. No. 12/723,589
→
READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION
App. No. 12/646,279
→
DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD
App. No. 12/635,148
→
CONTROL CIRCUIT FOR DC-DC CONVERTER, CONTROL METHOD FOR DC-DC CONVERTER, AND ELECTRONIC DEVICE
App. No. 12/617,253
→
DATA CONVERSION APPARATUS, METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM FOR GENERATING CIRCUIT CONFIGURATION INFORMATION FROM CIRCUIT DESCRIPTION
App. No. 12/503,455
→
DESIGN PROGRAM, DESIGN APPARATUS, AND DESIGN METHOD FOR DYNAMIC RECONFIGURABLE CIRCUIT
App. No. 12/497,022
→
AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING
App. No. 12/492,922
→
IMAGING DEVICE HAVING A RADIATION DETECTING STRUCTURE DISPOSED AT A SEMICONDUCTOR SUBSTRATE WITH A THERMALIZING MATERIAL AND A FIRST RADIATION-REACTIVE MATERIAL SENSITIVE TO NEUTRON RADIATION (AS AMENDED)
App. No. 12/472,735
→
CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE
App. No. 12/473,081
→
RADIATION DETECTING DEVICE AND METHOD OF OPERATING
App. No. 12/468,615
→
A CAPACITANCE SENSOR FOR DETECTING A CHARGE VOLTAGE OF A MULTI-CAPACITOR CIRCUIT
App. No. 12/401,174
→
POWER SUPPLY CONTROL DEVICE AND POWER SUPPLY CONTROL METHOD
App. No. 12/369,954
→
POWER SUPPLY CIRCUIT, OVERCURRENT PROTECTION CIRCUIT FOR THE SAME, AND ELECTRONIC DEVICE
App. No. 12/369,907
→
SYSTEMS AND METHODS FOR LOCATING ERROR BITS IN ENCODED DATA
App. No. 12/368,835
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/337,134
→
DC-DC CONVERTER, DC-DC CONVERTER CONTROL METHOD, AND ELECTRONIC DEVICE
App. No. 12/273,804
→
ERROR CORRECTION FOR FLASH MEMORY
App. No. 12/267,017
→
SEMICONDUCTOR DEVICE INCLUDING A PRESSURE-CONTACT SECTION
App. No. 12/234,337
→
ERROR CORRECTION SCHEME FOR NON-VOLATILE MEMORY
App. No. 12/139,650
→
CONNECTIONS FOR ELECTRONIC DEVICES ON DOUBLE-SIDED CIRCUIT BOARD
App. No. 12/080,311
→
DC-DC CONVERTER FOR PULSE FREQUENCY MODULATION CONTROL AND POWER SUPPLY SYSTEM
App. No. 12/049,941
→
MITIGATION OF FLASH MEMORY LATENCY AND BANDWIDTH LIMITATIONS VIA A WRITE ACTIVITY LOG AND BUFFER
App. No. 12/026,362
→
RELOCATING DATA IN A MEMORY DEVICE
App. No. 11/966,923
→
SYSTEM AND METHOD FOR OPTIMIZED ERROR CORRECTION IN FLASH MEMORY ARRAYS
App. No. 11/963,078
→
EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN
App. No. 11/960,601
→
CONVEX SHAPED THIN-FILM TRANSISTOR DEVICE
App. No. 12/002,728
→
DATA TRANSMISSION SYSTEM-ON-CHIP MEMORY MODEL BASED VALIDATION
App. No. 11/950,006
→
ERROR CORRECTION CODING IN FLASH MEMORY DEVICES
App. No. 11/928,434
→
LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE
App. No. 11/877,497
→
EXPOSURE SYSTEM, SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
App. No. 11/894,921
→
FULLY ASSOCIATIVE BANKING FOR MEMORY
App. No. 11/625,150
→
BYTE MASK COMMAND FOR MEMORIES
App. No. 11/625,158
→
SOLID-STATE MEMORY-BASED GENERATION AND HANDLING OF SECURITY AUTHENTICATION TOKENS
App. No. 11/614,306
→
SEMICONDUCTOR DEVICE WITH STOP LAYERS AND FABRICATION METHOD USING CERIA SLURRY
App. No. 11/480,207
→
MEMORY DEVICE WITH IMPROVED SWITCHING SPEED AND DATA RETENTION
App. No. 11/078,873
→
MICROCOMPUTER WITH INTERNAL DMA
App. No. 11/036,332
→