Local interconnect having increased misalignment tolerance
View Patent ↗A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.
1. A method comprising:
forming a pair of select transistors formed over a substrate;
forming a source region between the pair of select transistors formed over the substrate;
forming a silicide region over an upper surface of the source region;
forming spacers adjacent to interior sidewalls of the pair of select transistors;
depositing an inter-layer dielectric between the spacers; and
etching the inter-layer dielectric to form an interconnect area, where a width of the interconnect area is less than a distance between the pair of select transistors.
2. The method of claim 1 , further comprising:
forming a liner oxide layer over the pair of select transistors and the source region,
where the spacers are formed over the line oxide layer.
3. The method of claim 1 , further comprising:
forming a contact within the interconnect area.
4. The method of claim 1 , where the width of the interconnect area is between 40 nm and 60 nm less than the distance between the pair of select transistors.
5. The method of claim 1 , further comprising:
forming a barrier layer over the interconnect area,
where the barrier layer includes at least one of:
a titanium layer, or
a titanium nitride layer.
6. The method of claim 5 , where a thickness of the barrier layer ranges from about 50 Å to about 300 Å.
7. A method comprising:
forming a silicide region over an upper surface of a source region of a substrate, where a pair of select transistors are positioned on the substrate and on opposite sides of the source region;
depositing an inter-layer dielectric between spacers that are formed over adjacent interior sidewalls of the pair of select transistor; and
etching the inter-layer dielectric to form an interconnect area,
where a width of the interconnect area is less than a distance between the pair of select transistors.
8. The method of claim 7 , where the silicide region includes at least one of tungsten, cobalt, titanium, tantalum nickel or molybdenum, and
where a thickness of the silicide region ranges from about 50 Å to about 500 Å.
9. The method of claim 7 , further comprising:
forming a select transistor, of the pair of select transistors,
where forming the select transistor includes:
forming a first dielectric layer over the substrate,
forming a charge storage layer over the first dielectric layer,
forming a second dielectric layer over the charge storage layer, and
forming a control gate layer over the second dielectric layer.
10. The method of claim 9 , where the charge storage layer includes a silicon nitride layer, and
where a thickness of the silicon nitride layer ranges from about 25 Å to about 500 Å.
11. The method of claim 9 , where the control gate layer includes a polysilicon layer, and
where a thickness of the polysilicon layer ranges from about 1000 Å to about 2000 Å.
12. The method of claim 7 , further comprising:
forming a contact within the interconnect area.
13. The method of claim 7 , where the width of the interconnect area is between 40 nm and 60 nm less than the distance between the pair of select transistors.
14. A method comprising:
forming, on a substrate, select transistors on opposite sides of a source region within the substrate;
depositing an inter-layer dielectric between sidewall spacers of the select transistors; and
etching the inter-layer dielectric to form the interconnect area,
where a width of the interconnect area is less than a distance between the select transistors.
15. The method of claim 14 , where the width of the interconnect area is between 40 nm and 60 nm less than the distance between the select transistors.
16. The method of claim 14 , further comprising:
forming a silicide region on an upper surface of the source region.
17. The method of claim 16 , where the silicide region includes at least one of tungsten, cobalt, titanium, tantalum nickel or molybdenum, and
where a thickness of the silicide region ranges from about 50 Å to about 500 Å.
18. The method of claim 14 , further comprising:
forming a select transistor, of the select transistors,
where forming the select transistor includes:
forming a first dielectric layer on the substrate,
forming a charge storage layer on the first dielectric layer, and
forming a control gate layer formed over the charge storage layer.
19. The method of claim 18 , where the charge storage layer includes a silicon nitride layer, a thickness of the silicon nitride layer ranging from about 25 Å to about 500 Å, and
where the control gate layer includes a polysilicon layer, a thickness of the polysilicon layer ranging from about 1000 Å to about 2000 Å.
20. The method of claim 14 , further comprising:
forming a liner oxide layer over the select transistors and the source region,
where the sidewall spacers are formed over the line oxide layer.