IP Library Granted Patent US 8,273,627
Granted Patent B2
US 8,273,627 · App. 12/337,134 · Granted Sep 25, 2012

Semiconductor device and method for manufacturing thereof

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Quick Facts
Patent No.
US 8,273,627
App. No.
12/337,134
Granted
Sep 25, 2012
Kind
B2
Abstract

A semiconductor device which includes two trenches formed in a semiconductor substrate, a charge storage layer as an insulator formed on each side surface of the trenches, and separated on a bottom surface thereof, and a bit line formed below the bottom surface of the trenches in the semiconductor substrate. A channel region is formed in the semiconductor substrate from a side surface of one of the two trenches to that of the other trench via an upper surface of a protruding portion between those two trenches. A method for manufacturing the semiconductor device is also provided.

Claims (23)

1. A semiconductor device comprising:

two trenches formed in a semiconductor substrate, wherein each side surface of the two trenches is sloped;

a charge storage layer as an insulator formed on each of the sloped side surfaces of the two trenches, wherein each sloped side surface of the two trenches has a separate charge storage layer, wherein the charge storage layers are separated from each other by the bottom surfaces of the two trenches, and wherein each charge storage layer extends substantially an entire length of a corresponding sloped side surface; and

a bit line formed only below the bottom surface of each one of the two trenches inside the semiconductor substrate, wherein the bit lines are separated from respective side surface edges of each of the two trenches, wherein a channel region is formed in the semiconductor substrate from one side surface of one of the two trenches to that of the other trench via an upper surface of a protruding portion formed between the two trenches.

2. The semiconductor device according to claim 1 , wherein each one of the bit lines is defined by the charge storage layers which are separated from each other by the bottom surfaces of the two trenches.

3. The semiconductor device according to claim 1 , wherein the bit line is only formed between the respective side surfaces of each of the two trenches.

4. A method for manufacturing a semiconductor device comprising:

forming two trenches in a semiconductor substrate, wherein each side surface of the two trenches is sloped;

forming a charge storage layer as an insulator on each of the sloped side surfaces of the two trenches, wherein each sloped side surface of the two trenches has a separate charge storage layer, wherein the charge storage layers are separated from each other by the bottom surfaces of the two trenches, and wherein each charge storage layer extends substantially an entire length of a corresponding sloped side surface; and

forming a bit line only below each bottom surface of the two trenches inside the semiconductor substrate, wherein the bit lines are separated from respective side surface edges of each of the two trenches, wherein a channel region is formed in the semiconductor substrate from one side surface of one of the two trenches to that of the other trench via an upper surface of a protruding portion formed between the two trenches.

5. The method for manufacturing a semiconductor device according to claim 4 , further comprising forming a sidewall layer on a side surface of the charge storage layer formed on each side surface of the two trenches, wherein the step of forming the charge storage layer includes eliminating the charge storage layer formed on each bottom surface of the two trenches using the sidewall layer as a first mask.

6. The method for manufacturing a semiconductor device according to claim 5 , wherein the bit line is formed using the sidewall layer as the first mask.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the bit line is only formed between the respective side surfaces of each of the two trenches.

8. The method for manufacturing a semiconductor device according to claim 5 , wherein:

the two trenches are formed using a mask layer formed on the semiconductor substrate as a second mask;

the charge storage layer is formed on an inner surface of the two trenches and on side and upper surfaces of the mask layer; and

the sidewall layer is formed on the side surfaces of the two trenches.

9. The method for manufacturing a semiconductor device according to claim 8 , further comprising polishing the mask layer to eliminate the mask layer.

10. The method for manufacturing a semiconductor device according to claim 8 , wherein the mask layer is formed on the semiconductor substrate via a protection layer.

11. The method for manufacturing a semiconductor device according to claim 10 , further comprising selectively eliminating the mask layer with respect to the protection layer.

12. The method for manufacturing a semiconductor device according to claim 5 , wherein:

the step of forming the two trenches includes using a mask layer formed on the semiconductor substrate as a second mask; and

the step of forming the charge storage layer includes forming the charge storage layer on each inner surface of the two trenches after eliminating the mask layer.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
SECURITY AGREEMENT Recorded Aug 23, 2012
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 028837/0076 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2009
From: UTSUNO, YUKIHIRO
To: SPANSION LLC
Reel/Frame 022604/0442 →