IP Library Granted Patent US 8,222,147
Granted Patent B2
US 8,222,147 · App. 11/480,207 · Granted Jul 17, 2012

Semiconductor device with stop layers and fabrication method using ceria slurry

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Quick Facts
Patent No.
US 8,222,147
App. No.
11/480,207
Granted
Jul 17, 2012
Kind
B2
Abstract

The present invention provides a method of fabricating a semiconductor device including forming stop layers ( 32 ) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film ( 34 ) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers ( 30 ) provided above a semiconductor substrate, silicon oxy-nitride films ( 32 ) provided on the metal layers, and an embedded layer ( 36 ) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.

Claims (30)

1. A method of fabricating a semiconductor device comprising:

forming a silicon nitride film 100 nanometers thick above a semiconductor substrate;

forming stop layers that include silicon oxy-nitride films above the silicon nitride film, wherein the stop layers comprise a refractive index between 1.8-2.3 and an absorption coefficient between 0.1-1.5, and wherein the stop layers are 35 nanometers thick;

forming a cover film between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, wherein the cover film is an insulative layer; and

polishing the cover film to the stop layers by using ceria slurry.

2. The method as claimed in claim 1 , further comprising forming a trench in the semiconductor substrate, by etching the semiconductor substrate, wherein forming the cover film includes forming the cover film in the trench and on the stop layers, and wherein the cover film is directly in contact with the trench in the semiconductor substrate.

3. The method as claimed in claim 2 ,

wherein forming the stop layers includes etching a layer to become the stop layers; and

wherein forming the trench includes etching the semiconductor substrate by using a mask used for etching the stop layers.

4. The method as claimed in claim 3 , further comprising:

forming a silicon nitride layer by etching the silicon nitride film,

wherein forming the stop layers includes forming the stop layers on the silicon nitride layer; and wherein forming the trench includes etching the semiconductor substrate by using the mask used for etching the stop layers and the silicon nitride film.

5. The method as claimed in claim 4 , wherein the silicon nitride layer is removed by a phosphoric acid-based solution.

6. The method as claimed in claim 3 ,

wherein a photoresist film formed on the layer to become the stop layers is used as the mask used for forming the trench; and

wherein the layer to become stop layers is also used as an antireflective film for exposing the photoresist film.

7. The method as claimed in claim 6 , wherein the thickness of the layer to become stop layers is determined such that reflection is avoided during a normal lithography process.

8. The method as claimed in claim 6 , wherein a given region of the photoresist film is exposed through the lithography process and then removed during a photoresist development process.

9. The method as claimed in claim 1 , further comprising forming metal layers above the semiconductor substrate,

wherein forming the stop layers includes forming the stop layers on the metal layers; and

forming the cover film includes forming the cover film between the metal layers and on the stop layers.

10. The method as claimed in claim 9 , wherein forming the metal layers includes etching a metal film to become the metal layers by using a mask used for etching the stop layers.

11. The method as claimed in claim 1 , wherein the stop layer is removed by a hydrofluoric acid-based solution.

12. The method as claimed in claim 11 , wherein a faster etch rate of the stop layer with the hydrofluoric acid-based solution is employed so as to obtain an etching selectivity with a silicon nitride film during the removal of the stop layer.

13. A semiconductor device comprising:

metal layers provided above a semiconductor substrate;

silicon oxy-nitride films provided on and in direct contact with the metal layers, wherein the silicon oxy-nitride films comprise a refractive index between 1.8-2.3 and an absorption coefficient between 0.1-1.5, and wherein the silicon oxy-nitride films are 35 nanometers thick; and

an embedded layer provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films, wherein the embedded layer is an insulative layer, wherein a portion of the embedded layer extends into and directly contacts the semiconductor substrate, and wherein the embedded layer is polished using a ceria slurry.

14. The method as claimed in claim 13 , wherein the metal layers are 200-400 nanometers thick.

15. The semiconductor device as claimed in claim 13 , wherein the metal layers comprise polysilicon film.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2015
From: ENDA, TAKAYUKI; MORIYA, MASAYUKI
To: SPANSION, LLC
Reel/Frame 036591/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2006
From: ENDA, TAKAYUKI; MORIYA, MASAYUKI
To: SPANSION LLC
Reel/Frame 018213/0402 →