IP Library Granted Patent US 8,278,171
Granted Patent B2
US 8,278,171 · App. 13/081,777 · Granted Oct 2, 2012

Fabrication method for semiconductor device having laminated electronic conductor on bit line

Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,278,171
App. No.
13/081,777
Granted
Oct 2, 2012
Kind
B2
Abstract

There are provided a semiconductor device and a fabrication method therefor including an ONO film ( 18 ) formed on a semiconductor substrate ( 10 ), a word line ( 24 ) formed on the ONO film ( 18 ), a bit line ( 20 ) formed in the semiconductor substrate ( 10 ), and a conductive layer ( 32 ) that is in contact with the bit line ( 20 ), runs in a length direction of the bit line ( 20 ), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.

Claims (23)

1. A method of fabricating a semiconductor device comprising:

forming a tunnel oxide film and a trap layer overlaying the tunnel oxide film on a semiconductor substrate;

forming a bit line in the semiconductor substrate;

forming an opening in contact with the bit line in the tunnel oxide film and in the trap layer; and

forming a conductive layer in the opening and running in a length direction of the bit line, wherein the conductive layer runs substantially the entire length of the bit line, and wherein the conductive layer comprises a polysilicon layer or a metal layer in contact with the bit line.

2. The method as claimed in claim 1 , further comprising forming a protection film on the trap layer, wherein forming the opening includes forming the opening in the protection film.

3. The method as claimed in claim 2 , wherein forming the conductive layer includes:

forming the polysilicon layer or the metal layer on the protection film and in the opening; and

polishing the protection film and either the polysilicon layer or the metal layer.

4. The method as claimed in claim 3 , further comprising forming a metal silicide layer on the conductive layer.

5. The method as claimed in claim 4 , wherein forming the metal silicide layer includes forming a metal layer to be silicided on the conductive layer and on a silicon nitride film.

6. The method as claimed in claim 2 , further comprising:

removing the protection film; and

forming a top oxide film over the trap layer and the conductive layer.

7. The method as claimed in claim 6 , wherein forming the top oxide film comprises forming the top oxide film having a thickness less than that of the protection film.

8. The method as claimed in claim 6 , further comprising forming a word line on the top oxide film.

9. The method as claimed in claim 2 , further comprising forming a portion of an oxide film over the protection film and the conductive layer, wherein a top oxide film comprises the protection film and the portion of the oxide film.

10. The method as claimed in claim 1 , wherein forming the conductive layer includes:

forming the polysilicon layer or the metal layer in the opening and on the trap layer; and

etching the polysilicon layer or the metal layer in regions other than the opening.

11. The method as claimed in claim 10 , wherein a width of the conductive layer is greater than that of the tunnel oxide film and the trap layer.

12. The method as claimed in claim 10 , further comprising forming a metal silicide layer on the conductive layer.

13. The method as claimed in claim 1 , wherein forming the opening includes etching the trap layer and the tunnel oxide film by using a mask layer and sidewalls as an etching mask, wherein the mask layer is provided above the trap layer, and wherein the sidewalls are formed at both sides of an opening in the mask layer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 19, 2019
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 051334/0633 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LIMITED
Reel/Frame 051251/0787 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Priority Claims (1)
WO PCT/JP2005/009878 · May 30, 2005 · international
Continuity (3)
Division 11444216 · May 30, 2006
Continuation PCTJP2005009878 · May 30, 2005
Related Publication 20110183510A1 · Jul 28, 2011