Process margin engineering in charge trapping field effect transistors
View Patent ↗Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.
1. A method comprising:
forming a plurality of shallow trench isolation regions on a substrate;
forming a tunneling dielectric region on a substrate;
forming a first nitride layer on the tunneling dielectric region and shallow trench isolation regions;
etching back a portion of the first nitride layer to the tops of the trench isolation regions;
forming a second nitride layer on the etched back first nitride layer;
oxidizing portions of the first and second nitride layers to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region; and
forming a gate region on the blocking dielectric region.
2. The method according to claim 1 , wherein the first nitride layer comprises a silicon-rich-nitride layer.
3. The method according to claim 1 , wherein the second nitride layer comprises a silicon-rich-nitride layer.
4. The method according to claim 1 , wherein the charge trapping region comprises silicon nitride.
5. The method according to claim 1 , wherein the tunneling dielectric region comprises silicon oxide.
6. The method according to claim 1 , wherein the blocking dielectric region comprises silicon oxynitride.
7. The method according to claim 1 , wherein the blocking dielectric region comprises oxynitride.
8. A method comprising:
forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount;
oxidizing a portion of the substrate to form a blocking dielectric region;
depositing a first set of one or more nitride layers on the blocking dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount;
etching back a portion of the first set of one or more nitride layers to the tops of the trench isolation regions;
depositing a second set of one or more nitride layers on the etched back first set of one or more nitride layers;
oxidizing the second set of one or more nitride layers to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region; and
depositing a gate region on the blocking dielectric region.
9. The method according to claim 8 , wherein forming the shallow trench isolation regions comprises:
etching a plurality of trenches;
depositing a dielectric layer in the trenches; and
etching back the dielectric layer to form the shallow trench isolation regions in the trenches.
10. The method according to claim 8 , wherein depositing the first set of one or more nitride layers comprises chemical vapor depositing a first silicon-rich-nitride layer.
11. The method according to claim 10 , wherein depositing the second set of one or more nitride layers comprises chemical vapor depositing a second silicon-rich-nitride layer.
12. The method according to claim 8 , wherein the charge trapping region comprises silicon nitride.
13. The method according to claim 8 , wherein the blocking dielectric region comprises silicon oxynitride.
14. The method according to claim 8 , wherein the blocking dielectric region comprises oxynitride.
15. A method comprising:
forming a plurality of shallow trench isolation regions on a substrate having a mesa height that extends above the substrate by a given amount;
forming a tunneling dielectric region on a substrate;
forming a first nitride layer on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first nitride layer is approximately half of given amount;
etching back a portion of the first nitride layer to the tops of the mesas of the trench isolation regions to form a charge trapping region between the trenches;
forming a second nitride layer on the charge trapping region and the tops of the mesas of the trench isolation regions;
oxidizing the second nitride layer to form a blocking dielectric region on the charge trapping region; and
forming a gate region on the blocking dielectric region.
16. The method according to claim 15 , wherein forming the first nitride layer comprises chemical vapor depositing a silicon-rich-nitride layer.
17. The method according to claim 15 , wherein forming the second nitride layer comprises chemical vapor depositing a silicon nitride or silicon oxynitride layer.
18. The method according to claim 15 , wherein forming the gate region comprises chemical vapor depositing a polysilicon.
19. The method according to claim 15 , wherein forming the tunneling dielectric region comprises oxidizing a portion of the substrate.
20. The method according to claim 15 , wherein forming the shallow trench isolation regions comprises:
etching a plurality of trenches;
depositing a dielectric layer in the trenches; and
etching back the dielectric layer to form the shallow trench isolation regions in the trenches.