IP Library Granted Patent US 8,269,343
Granted Patent B2
US 8,269,343 · App. 12/234,337 · Granted Sep 18, 2012

Semiconductor device including a pressure-contact section

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,269,343
App. No.
12/234,337
Granted
Sep 18, 2012
Kind
B2
Abstract

A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.

Claims (50)

1. A semiconductor device comprising:

a substrate onto which a wiring pattern is formed;

a plurality of semiconductor packages wherein each semiconductor package comprises a lead frame that is connected to an electrode of a semiconductor chip and the lead frame is located on a side surface and a bottom surface of the semiconductor package; and

a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.

2. The semiconductor device of claim 1 , wherein the pressure-contact section comprises:

a depressing section that depresses an uppermost semiconductor package of the plurality of semiconductor packages towards the substrate; and

a positioning section that engages with the substrate to position a lowermost semiconductor package onto the wiring pattern.

3. The semiconductor device of claim 1 , wherein the pressure-contact section comprises:

a conductive section that is coupled with the wiring pattern; and

a first holding section for each lead frame of the plurality of semiconductor packages.

4. The semiconductor device of claim 2 , wherein each lead frame of the plurality of semiconductor packages comprises a part that extends from the side surface towards an upper surface of each semiconductor package; and

wherein the semiconductor device further comprises a case that is formed by integrating the depressing section and the positioning section.

5. The semiconductor device of claim 4 , wherein the plurality of semiconductor packages are stacked in a manner that each lead frame located on the bottom is arranged upward and the part of each lead frame that extends toward the upper surface of each semiconductor package is arranged downward.

6. The semiconductor device of claim 5 , wherein the case comprises a side plate that comprises a fastener for engaging a lower surface of the substrate.

7. The semiconductor device of claim 2 , wherein:

each lead frame of the plurality of semiconductor packages is also located on a top surface of each semiconductor package;

the positioning section comprises a bolt coupled to a lower surface of the substrate; and

the depressing section comprises an adjustable nut that couples to the bolt and adjusts a force to the uppermost semiconductor package.

8. The semiconductor device of claim 1 , wherein each lead frame of the plurality of semiconductor packages comprises a part that extends from the bottom surface towards the side surface of each semiconductor package, the part for moving toward the side surface.

9. A method for manufacturing a semiconductor device, comprising:

manufacturing a substrate onto which a wiring pattern is formed;

manufacturing a plurality of semiconductor packages wherein each semiconductor package comprises a lead frame that is connected to an electrode of a semiconductor chip and the lead frame is located on a side surface and a bottom surface of the semiconductor package;

causing the plurality of semiconductor packages to come into contact with the wiring pattern via a pressure-contact section of said semiconductor device.

10. The method of claim 9 , wherein the causing comprises:

depressing an uppermost semiconductor package of the plurality of semiconductor packages towards the substrate such that a lowermost semiconductor package comes into contact with the wiring pattern.

11. The method of claim 9 , wherein the causing comprises:

abutting each lead frame of each semiconductor package against a conductor coupled to the wiring pattern.

12. The method of claim 9 , wherein the plurality of semiconductor packages are stacked in a manner that each lead frame located on the bottom is arranged upward and the part of each lead frame that extends toward the upper surface of each semiconductor package is arranged downward.

13. The method of claim 12 , wherein the semiconductor device further comprises a case that comprises a fastener.

14. The method of claim 13 , further comprising:

engaging the case to a low surface of the substrate via the fastener.

15. The method of claim 9 , wherein the pressure-contact section comprises:

a depressing section that depresses an uppermost semiconductor package of the plurality of semiconductor packages towards the substrate; and

a positioning section that engages with the substrate to position a lowermost semiconductor package onto the wiring pattern.

16. The method of claim 15 , wherein each lead frame of the plurality of semiconductor packages comprises a part that extends from the side surface towards an upper surface of each semiconductor package; and

wherein the semiconductor device further comprises a case that is formed by integrating the depressing section and the positioning section.

17. A semiconductor device comprising:

a substrate onto which a wiring pattern is formed;

a plurality of semiconductor packages wherein each semiconductor package comprises a lead frame that is connected to an electrode of a semiconductor chip and the lead frame is located on a side surface and a bottom surface of the semiconductor package, wherein the semiconductor chip comprises a flip chip; and

a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.

18. The semiconductor device of claim 17 , wherein the pressure-contact section comprises:

a depressing section that depresses an uppermost semiconductor package of the plurality of semiconductor packages towards the substrate; and

a positioning section that engages with the substrate to position a lowermost semiconductor package onto the wiring pattern.

19. The semiconductor device of claim 18 , wherein:

each lead frame of the plurality of semiconductor packages is also located on a top surface of each semiconductor package;

the positioning section comprises a bolt coupled to a lower surface of the substrate; and

the depressing section comprises an adjustable nut that couples to the bolt and adjusts a force to the uppermost semiconductor package.

20. The semiconductor device of claim 17 , wherein the pressure-contact section comprises:

a conductive section that is coupled with the wiring pattern; and

a first holding section for each lead frame of the plurality of semiconductor packages.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: MEGURO, KOUICHI
To: SPANSION LLC
Reel/Frame 021949/0455 →