Method for containing a silicided gate within a sidewall spacer in integrated circuit technology
View Patent ↗A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a contact is formed to the gate silicide.
1. A method of forming an integrated circuit comprising:
providing a semiconductor substrate;
forming a gate over the semiconductor substrate;
forming a sidewall spacer around the gate;
depositing a resist on the gate sidewall spacer with the gate sidewall spacer and the gate exposed;
removing a portion of the gate within the gate sidewall spacer;
forming a gate silicide substantially within the sidewall spacer;
depositing a liner layer in direct contact with the sidewall spacer and the gate silicide;
depositing a dielectric layer over the gate silicide; and
forming a contact in the dielectric layer to the gate silicide.
2. The method as claimed in claim 1 wherein depositing the liner layer includes depositing the liner layer over the gate silicide.
3. The method as claimed in claim 1 further comprising:
forming a source or drain silicide on the semiconductor substrate; and
forming an additional contact in the dielectric layer to the source or drain silicide.
4. The method as claimed in claim 1 wherein:
removing a thickness of the gate below the top of the sidewall spacer at least equal to the thickness of the gate silicide.
5. The method as claimed in claim 1 wherein:
removing a total thickness of the gate substantially equal to the thickness of the gate above the sidewall spacer plus the thickness of the gate silicide.
6. The method as claimed in claim 1 wherein:
forming the gate silicide includes depositing metal or metal and silicon to a thickness substantially equal to the portion of the gate removed within the gate sidewall spacer.
7. The method as claimed in claim 1 wherein:
forming the gate silicide uses a material selected from a group consisting of tantalum, titanium, tungsten, copper, gold, silver, an alloy thereof, a compound thereof, and a combination thereof.
8. A method of forming an integrated circuit comprising:
providing a semiconductor substrate;
forming first and second gate dielectrics on the semiconductor substrate;
forming first and second gates respectively on the first and second gate dielectrics;
forming a single curved gate sidewall spacer around the first and second gates;
depositing a resist on the single curved gate sidewall spacer with the single curved gate sidewall spacer and the first and second gates exposed;
removing portions of the first and second gates below the top of the single curved gate sidewall spacer;
forming first and second gate silicides within the single curved gate sidewall spacer respectively over the first and second gates;
depositing a liner layer in direct contact with the single curved gate sidewall spacer and the first and second gate silicide;
depositing a dielectric layer over the first and second gate silicides; and
forming a contact to the semiconductor substrate.
9. The method as claimed in claim 8 wherein depositing the liner layer includes depositing the liner layer over the first and second gate silicides.
10. The method as claimed in claim 8 further comprising:
forming a source or drain silicide on the semiconductor substrate;
forming an additional contact to the source or drain silicide; and
forming a first contact to the first gate silicide.
11. The method as claimed in claim 8 wherein:
removing a thickness of the gate below the top of the gate sidewall spacer equal to the thickness of the gate silicide.
12. The method as claimed in claim 8 wherein:
removing a total thickness of the gate equal to the thickness of the gate above the gate sidewall spacer plus the thickness of the gate silicide.
13. The method as claimed in claim 8 wherein:
forming the gate silicide includes depositing metal or metal and silicon to a thickness equal to the portion of the gate removed within the gate sidewall spacer.
14. The method as claimed in claim 8 wherein:
forming the gate silicide uses a refractory material.
15. An integrated circuit comprising:
a semiconductor substrate;
first and second gate dielectrics over the semiconductor substrate;
a first and second gates on the first and second gate dielectrics;
a single curved gate sidewall spacer around the first and second gates;
first and second gate silicides substantially within the single curved gate sidewall spacer and respectively over the first and second gates;
a liner layer deposited in direct contact with the single curved gate sidewall spacer and the first and second gate silicides;
a dielectric layer over the first and second gate silicides; and
a gate contact to the first gate silicide.
16. The integrated circuit as claimed in claim 15 further comprising:
an additional gate contact to the second gate silicide;
a source or drain silicide on the semiconductor substrate; and
a contact to the source or drain silicide.
17. The integrated circuit as claimed in claim 15 wherein:
the gate silicides are below the tops of the single curved sidewall spacer.
18. The integrated circuit as claimed in claim 15 wherein:
the gate dielectric, the gate, and the gate silicide are below the top of the single curved sidewall spacer.
19. The integrated circuit as claimed in claim 15 wherein:
the gate silicide is a refractory silicide.