IP Library Granted Patent US 8,225,172
Granted Patent B2
US 8,225,172 · App. 12/139,650 · Granted Jul 17, 2012

Error correction scheme for non-volatile memory

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Quick Facts
Patent No.
US 8,225,172
App. No.
12/139,650
Granted
Jul 17, 2012
Kind
B2
Abstract

Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level.

Claims (21)

1. A non-volatile memory device comprising:

a data area for storing data;

an error correcting code (ECC) generation section for generating an error correcting code in response to receipt of a code generation command;

an error correcting code area for storing the error correcting code;

a detector circuit for detecting the generated error correcting code; and

a read section for repairing the data stored in the data area based on the error correcting code upon the detecting of the generated error correcting code by the detector circuit,

wherein the code generation command is forwarded by a memory controller when the data area is filled with the data beyond a threshold level.

2. The non-volatile memory device according to claim 1 , wherein the error correcting code generation section generates a flag information in conjunction with the generating of the error correcting code.

3. The non-volatile memory device according to claim 2 , wherein the detector circuit detects the generated error correcting code in response to the flag information.

4. The non-volatile memory device according to claim 2 , wherein the error correcting code area stores the flag information.

5. The non-volatile memory device according to claim 4 , wherein the detector circuit receives the flag information from the error correcting code area.

6. The non-volatile memory device according to claim 1 ,

wherein the detector circuit outputs a detection result representing that the error correcting code has not been generated when every bit of the error correcting code is the same, and

the detector circuit outputs a detection result representing that the error correcting code has been generated when at least one bit of the error correcting code is different from remaining bits of the error correcting code.

7. The non-volatile memory device according to claim 1 , wherein the error correcting code generation section comprises:

a code generation circuit that generates the error correcting code;

a buffer; and

an input path that forwards the data stored in the data area to the buffer in response to the code generation command.

8. The non-volatile memory device according to claim 7 , wherein the buffer combines additional data written to the data area with the data stored in the data area forwarded to the buffer via the input path in response to the receipt of the code generation command, wherein combined data of the additional data and the data stored in the data area are forwarded to the code generation circuit.

9. The non-volatile memory device according to claim 1 , wherein the read section comprises a correction circuit that repairs the data stored in the data area based on the error correcting code.

10. The non-volatile memory device according to claim 9 , wherein the read section further comprises a selector that receives a first output from the correction circuit and a second output from the data area, with the selector circuit selecting the second output when receiving a notification from the detector circuit that the error correcting code has not been generated, and with the selector selecting the first output when receiving notification from the detector circuit that the error correcting code has been generated.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2008
From: KASA, YASUSHI
To: SPANSION LLC
Reel/Frame 021307/0538 →