IP Library Granted Patent US 8,203,817
Granted Patent B2
US 8,203,817 · App. 12/369,907 · Granted Jun 19, 2012

Power supply circuit, overcurrent protection circuit for the same, and electronic device

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Quick Facts
Patent No.
US 8,203,817
App. No.
12/369,907
Granted
Jun 19, 2012
Kind
B2
Abstract

A power supply circuit includes an output transistor including a source coupled to power supply voltage, and a drain from which output voltage is outputted; a first error amplifier powered by the power supply voltage and outputting a signal based on a potential difference between the output voltage and a reference voltage; a buffer transistor including a gate coupled to the output of the first error amplifier, and a source coupled via a constant current source to the power supply voltage and coupled to a gate of the output transistor; a current detection transistor coupled to the output transistor such that a gate and source are shared; and an overcurrent protection circuit configured to limit the drain current of the buffer transistor based on the increase of the drain current of the current detection transistor and thereby control the output current of the output transistor.

Claims (35)

1. A power supply circuit comprising:

an output transistor including a source coupled to a power supply voltage, and a drain from which output voltage is outputted;

a first error amplifier, powered by the power supply voltage, and outputting a signal based on a potential difference between the output voltage and a reference voltage;

a buffer transistor including a gate coupled to the output of the first error amplifier, and a source coupled via a constant current source to the power supply voltage and coupled to a gate of the output transistor;

a current detection transistor coupled to the output transistor such that a gate and source are shared; and

an overcurrent protection circuit configured to limit the drain current of the buffer transistor based on the increase of the drain current of the current detection transistor and thereby control the output current of the output transistor.

2. The power supply circuit according to claim 1 , wherein the overcurrent protection circuit includes:

a first resistor coupled to a drain of the current detection transistor; and

a first transistor including a gate that is biased to a constant voltage, a source provided between the drain of the current detection transistor and the first resistor, and a drain coupled to a drain of the buffer transistor.

3. The power supply circuit according to claim 1 , wherein:

the overcurrent protection circuit includes a first current mirror circuit including an input terminal coupled to the drain of the current detection transistor, and a second current mirror circuit including an output terminal coupled to the drain of the buffer transistor; and

an output terminal of the first current mirror circuit and an input terminal of the second current mirror circuit are coupled to each other and coupled via a constant current source to the power supply voltage.

4. The power supply circuit according to claim 2 , wherein the overcurrent protection circuit further includes:

a second resistor coupled in series to the first resistor;

a second error amplifier that outputs a voltage based on a potential difference between the output voltage and a certain voltage; and

a second transistor including a gate coupled to the output of the second error amplifier, and a drain provided between the first resistor and the second resistor.

5. An overcurrent protection circuit for a power supply circuit, comprising:

an output transistor including a source coupled to power supply voltage, and a drain from which output voltage is outputted; a first error amplifier, powered by the power supply voltage, and outputting a signal based on a potential difference between the output voltage and a reference voltage; and a buffer transistor including a gate coupled to the output of the first error amplifier, and a source coupled via a constant current source to the power supply voltage and at the same time coupled to a gate of the output transistor, wherein:

there is included a current detection transistor coupled to the output transistor such that the gate and source are shared; and

the first error amplifier drives the output transistor via the buffer transistor so that the output voltage is kept constant, and limits the drain current of the buffer transistor based on the increase of the drain current of the current detection transistor and thereby controls the output current of the output transistor.

6. The overcurrent protection circuit according to claim 5 , further comprising:

a first resistor coupled to a drain of the current detection transistor; and

a first transistor including a gate that is biased to a constant voltage, a source provided between the drain of the current detection transistor and the first resistor, and a drain coupled to a drain of the buffer transistor.

7. The overcurrent protection circuit according to claim 5 , further comprising:

a first current mirror circuit including an input terminal coupled to the drain of the current detection transistor; and

a second current mirror circuit including an output terminal coupled to the drain of the buffer transistor,

wherein an output terminal of the first current mirror circuit and an input terminal of the second current mirror circuit are coupled to each other and at the same time coupled via a constant current source to the power supply voltage.

8. The overcurrent protection circuit according to claim 6 , further comprising:

a second resistor coupled in series to the first resistor;

a second error amplifier that outputs a voltage based on a potential difference between the output voltage and a certain voltage; and

a second transistor including a gate coupled to the output of the second error amplifier, and a drain provided between the first resistor and the second resistor.

9. An electronic device comprising:

a power supply circuit that includes an output transistor including a source coupled to power supply voltage, and a drain from which output voltage is outputted; a first error amplifier, powered by the power supply voltage, and outputting a signal based on a potential difference between the output voltage and a reference voltage; and a buffer transistor including a gate coupled to the output of the first error amplifier, and a source coupled via a constant current source to the power supply voltage and at the same time coupled to a gate of the output transistor;

a load circuit coupled to an output terminal of the power supply circuit; and

an overcurrent protection circuit that includes a current detection transistor coupled to the output transistor such that a gate and source are shared; and limits the drain current of the buffer transistor based on the increase of the drain current of the current detection transistor and thereby controls output current supplied to the load circuit.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Sep 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 025046/0478 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2009
From: HASEGAWA, MORIHITO; ITO, HIDENOBU; HUI, KWOK FAI; KASAI, TOSHIHIKO; YASUKOUCHI, KATSUYUKI
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 022249/0452 →