Fabricating method of mirror bit memory device having split ONO film with top oxide film formed by oxidation process
View Patent ↗A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer.
1. A method of fabricating a charge trapping component of a memory, comprising the steps of:
forming a layered stack on a substrate such that the layered stack comprises an polysilicon layer, a charge trapping layer positioned between the polysilicon layer and the substrate, and a tunneling layer positioned between the charge trapping layer and the substrate;
patterning the layered stack to form a charge trapping element that includes a portion of the layered stack and another charge trapping element that includes another portion of the layered stack; and
forming a gate oxide layer by oxidizing a portion of the substrate between the charge trapping element and the other charge trapping element such that the polysilicon layer is converted into a polyoxide, wherein forming the layered stack is done such that the polysilicon layer is abutting the charge trapping layer.
2. The method of claim 1 , wherein forming the gate oxide layer includes thermally oxidizing the polysilicon layer such that the polyoxide layer forms an interface with the charge trapping layer.
3. The method of claim 1 , wherein patterning the layered stack includes defining a gate oxide region of at least one of a dual bit flash memory cell or a multi-bit flash memory cell.
4. The method of claim 1 , further comprising:
patterning the layered stack to form at least one trench in the layered stack; and
forming an isolation dielectric in the trench of the layered stack.
5. The method of claim 1 , further comprising patterning the layered stack to define a location of a source/drain region.
6. The method of claim 1 , further comprising forming a word line that extends above, at least, the gate oxide and the layered stack.
7. A device, comprising:
the charge trapping component fabricated by the method of claim 1 .
8. The method of claim 1 , wherein forming the gate oxide includes oxidizing the polysilicon layer such that the polysilicon layer of the layered stack is converted into a polyoxide layer positioned on top of the charge trapping layer.
9. A method of fabricating a charge trapping component of a memory, comprising the steps of:
forming a layered stack on a substrate such that the layered stack comprises an polysilicon layer, a charge trapping layer positioned between the polysilicon layer and the substrate, and a tunneling layer positioned between the charge trapping layer and the substrate;
patterning the layered stack to form a charge trapping element that includes a portion of the layered stack and another charge trapping element that includes another portion of the layered stack; and
forming a gate oxide layer by oxidizing a portion of the substrate between the charge trapping element and the other charge trapping element such that the polysilicon layer is converted into a polyoxide, wherein forming the gate oxide includes oxidizing the polysilicon layer for a duration of time such that the polysilicon of the polysilicon layer is fully consumed.
10. The method of claim 9 , wherein forming the layered stack is done such that the polysilicon layer is abutting the charge trapping layer.
11. A method of fabricating a charge trapping component of a memory, comprising the steps of:
forming a layered stack on a substrate such that the layered stack comprises an polysilicon layer, a charge trapping layer positioned between the polysilicon layer and the substrate, and a tunneling layer positioned between the charge trapping layer and the substrate;
patterning the layered stack to form a charge trapping element that includes a portion of the layered stack and another charge trapping element that includes another portion of the layered stack; and
forming a gate oxide layer by oxidizing a portion of the substrate between the charge trapping element and the other charge trapping element such that the polysilicon layer is converted into a polyoxide, wherein the tunneling layer includes a silicon oxide layer, and wherein patterning the layered stack includes:
etching the layered stack with at least one etch process such that a portion of the polysilicon layer and a portion of the charge trapping layer are removed from the layered stack; and
etching the layered stack with another etch process such that a portion of the silicon oxide layer is removed from the layered stack, wherein the other etch process is less selective to the silicon oxide layer than the at least one etch process.
12. A method of fabricating a charge trapping component of a memory, comprising the steps of:
forming a layered stack on a substrate such that the layered stack comprises an polysilicon layer, a charge trapping layer positioned between the polysilicon layer and the substrate, and a tunneling layer positioned between the charge trapping layer and the substrate;
patterning the layered stack to form a charge trapping element that includes a portion of the layered stack and another charge trapping element that includes another portion of the layered stack; and
forming a gate oxide layer by oxidizing a portion of the substrate between the charge trapping element and the other charge trapping element such that the polysilicon layer is converted into a polyoxide, wherein forming the gate oxide includes oxidizing the polysilicon layer such that the polysilicon layer of the layered stack is converted into a polyoxide layer, where the polyoxide layer is an isolation layer, and such that the charge trapping element is positioned between the polyoxide layer and the tunneling layer.
13. A method of fabricating a charge trapping component of a memory, comprising the steps of:
forming a layered stack on a substrate such that, the layered stack comprises an polysilicon layer, a charge trapping layer positioned between the polysilicon layer and the substrate, and a tunneling layer positioned between the charge trapping layer and the substrate;
patterning the layered stack to form a charge trapping element that includes a portion of the layered stack and another charge trapping element that includes another portion of the layered stack; and
forming a gate oxide layer by oxidizing a portion of the substrate between the charge trapping element and the other charge trapping element such that the polysilicon layer is converted into a polyoxide, wherein forming the gate oxide includes oxidizing the polysilicon layer such that the polysilicon layer of the layered stack is converted into a polyoxide layer, such that the layer stack is converted into an oxide-nitride-oxide (ONO) layer in which the polyoxide layer is the top oxide layer of the ONO layer.