SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same

1. A method for forming a memory cell, comprising:

forming a source-drain structure in a semiconductor substrate wherein said source-drain structure includes a rounded top surface and sidewall surfaces; and

forming an oxide layer on said top surface and said sidewall surfaces of said source-drain structure, wherein the thickness of a portion of said oxide layer that is formed on said top surface of said source-drain structure is greater than the thickness of portions of said oxide layer that are formed on said sidewall surfaces of said source-drain structure and a conduction region of said source-drain structure is orthogonal to a direction from one sidewall surface of said source-drain structure to the other and comprises the area between said one sidewall surface of said source-drain structure and said other.

2. The method of claim 1 wherein said thickness of said portion of said oxide layer formed on said top surface of said source-drain structure is at least 1.5 times the thickness of said portion of said oxide layer formed on said sidewall surfaces of said source-drain structure.

3. The method of claim 1 wherein said memory cell is less than 40 nm in width.

4. The method of claim 1 wherein said forming said oxide layer on said top surface and said sidewall surfaces of said source-drain structure comprises forming a first oxide layer on said top surface and said sidewall surfaces of said source-drain structure, forming a patterning layer above said first oxide layer, removing said patterning layer and portions of said first oxide layer formed on said sidewall surfaces of said source-drain structure and forming a second oxide layer above said first oxide layer and on said sidewall surfaces of said source-drain structure.

5. The method of claim 1 wherein said forming said memory cell is a part of the formation of a plurality of memory cells that comprise coupled charge trapping layers comprising silicon rich nitride.

6. The method of claim 1 wherein said source-drain structure is associated with the fabrication of an individual charge storage cell.

7. The method of claim 1 wherein said source-drain structure is fabricated from a semiconductor wafer.

8. A method for forming a memory array comprising:

forming a semiconductor substrate; and

forming a plurality of storage elements on said semiconductor substrate, comprising:

forming a source-drain structure in a semiconductor substrate wherein said source-drain structure includes a rounded top surface and sidewall surfaces;

forming a first oxide layer on said top surface and said sidewall surfaces of said source-drain structure, wherein the thickness of a portion of said first oxide layer that is formed on said top surface of said source-drain structure is greater than the thickness of a portion of said first oxide layer that is formed on said sidewall surfaces of said source-drain structure and a conduction region of said source-drain structure is orthogonal to a direction from one sidewall surface of said source-drain structure to the other and comprises the area between said one sidewall surface of said source-drain structure and said other;

forming a charge storage layer on said first oxide layer;

forming a second oxide layer on said charge storage layer; and

forming a polysilicon layer on said second oxide layer.

9. The method of claim 8 wherein said thickness of said portion of said first oxide layer formed on said top surface of said source-drain structure is at least 1.5 times the thickness of said portion of said first oxide layer formed on said sidewall surfaces of said source-drain structure.

10. The method of claim 8 wherein said memory cell is less than 40 nm in width.

11. The method of claim 8 wherein said forming said oxide layer on said top surface and said sidewall surfaces of said source-drain structure comprises forming a first oxide layer on said top surface and said sidewall surfaces of said source-drain structure, forming a patterning layer above said first oxide layer, removing said patterning layer and portions of said first oxide layer formed on said sidewall surfaces of said source-drain structure and forming a second oxide layer above said first oxide layer and on said sidewall surfaces of said source-drain structure.

12. The method of claim 8 wherein said forming a plurality of storage elements comprises the formation of a plurality of storage elements that comprise coupled charge storage layers comprising silicon rich nitride.

13. The method of claim 8 wherein said source-drain structure is associated with the fabrication of an individual charge storage cell.

14. The method of claim 8 wherein said source-drain structure is fabricated from a semiconductor wafer.