IP Library Granted Patent US 8,361,857
Granted Patent B2
US 8,361,857 · App. 13/323,370 · Granted Jan 29, 2013

Semiconductor device having a simplified stack and method for manufacturing thereof

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Quick Facts
Patent No.
US 8,361,857
App. No.
13/323,370
Granted
Jan 29, 2013
Kind
B2
Abstract

Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.

Claims (9)

1. A method for manufacturing a semiconductor device comprising:

forming, in a semiconductor wafer comprising a first region and a second region, a portion of the second region into a plurality of connector terminals;

electrically insulating the first region from the plurality of connector terminals; and

electrically coupling the first region with the plurality of connector terminals,

wherein the first region is formed into a semiconductor chip and the second region is disposed around the first region and is formed into said connector terminals wherein said semiconductor chip and said connector terminals are formed of the same material.

2. The method according to claim 1 , wherein the semiconductor wafer comprises a conductive material.

3. The method according to claim 1 , wherein forming the portion of the second region into a plurality of connector terminals comprises forming a groove between the first region and the second region of the semiconductor wafer such that the first region and the second region are not directly in contact with each other.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein electrically insulating the first region from the connector terminal comprises filling the groove with an insulating member.

5. The method for manufacturing a semiconductor device according to claim 4 , wherein electrically insulating the first region from the connector terminal further comprises coating side surfaces of the semiconductor chip and the connector terminal with the insulating member.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2025
From: MONTEREY RESEARCH LLC
To: SOUTHFORK IP HOLDINGS LLC
Reel/Frame 071299/0161 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0786 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →