Patent Assignment
Reel/Frame 071299/0161
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2025-05-16
Received: 2025-05-16
Pages: 8
Assignor
MONTEREY RESEARCH LLC
Executed: 2025-01-31
Assignee
SOUTHFORK IP HOLDINGS LLC
3101 BOARDWALK, UNIT 3403 T2, ATLANTIC CITY, NJ, 08401, UNITED STATES
Covered Applications
(74)
FAST RAMP LOW SUPPLY CHARGE PUMP CIRCUITS
App. No. 15/717,457
→
Interrupt latency reduction
App. No. 14/319,041
→
MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION BY PREFERENTIALLY STORING FREQUENTLY WRITTEN SECTORS IN CACHE MEMORY DURING A DATABURST
App. No. 14/269,299
→
HARDWARE BASED WEAR LEVELING MECHANISM FOR FLASH MEMORY USING A FREE LIST
App. No. 13/670,910
→
VISUAL INDICATION OF A DEVICE CONNECTION SPEED
App. No. 13/324,952
→
SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/323,370
→
BUSY DETECTION LOGIC FOR ASYNCHRONOUS COMMUNICATION PORT
App. No. 13/154,348
→
CLOCKING ANALOG COMPONENTS OPERATING IN A DIGITAL SYSTEM
App. No. 13/103,862
→
CIRCUIT, SYSTEM AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER
App. No. 13/038,028
→
OUTPUT BUFFER CIRCUIT
App. No. 13/013,725
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DRIVER CIRCUIT AND ADJUSTMENT METHOD THEREFOR
App. No. 12/826,317
→
MEMORY SYSTEM AND METHOD
App. No. 12/819,794
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ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES
App. No. 12/723,589
→
ENABLING MULTIPLE DEVICES USING A SINGLE BUS BRIDGE
App. No. 12/689,857
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PLL CIRCUIT AND OSCILLATOR DEVICE
App. No. 12/617,234
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CIRCUIT, SYSTEM, AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER
App. No. 12/577,477
→
CLOCKING ANALOG COMPONENTS OPERATING IN A DIGITAL SYSTEM
App. No. 12/533,772
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METHOD AND APPARATUS FOR DYNAMICALLY DETECTING ENVIRONMENTAL CONDITIONS AND ADJUSTING DRIVE STRENGTH IN RESPONSE TO THE DETECTING
App. No. 12/509,249
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REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY
App. No. 12/433,499
→
SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/341,863
→
RESET SIGNAL GENERATION CIRCUIT
App. No. 12/289,030
→
METHOD AND SYSTEM OF DIGITAL SIGNAL PROCESSING
App. No. 12/238,893
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MEMORY SYSTEM AND METHOD
App. No. 12/239,532
→
COMMAND CONTROL FOR SYNCHRONOUS MEMORY DEVICE
App. No. 12/138,307
→
REPLICA TRANSISTOR VOLTAGE REGULATOR
App. No. 12/154,169
→
INTERRUPT LATENCY REDUCTION
App. No. 12/075,632
→
BUSY DETECTION LOGIC FOR ASYNCHRONOUS COMMUNICATION PORT
App. No. 12/044,831
→
ENABLING MULTIPLE ATA DEVICES USING A SINGLE BUS BRIDGE
App. No. 12/031,558
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PARTIAL ALLOCATE PAGING MECHANISM USING A CONTROLLER AND A BUFFER
App. No. 12/026,302
→
WEAR LEVELING MECHANISM USING A DRAM BUFFER
App. No. 12/026,299
→
DISPLAY INTERFACE BUFFER
App. No. 11/965,485
→
VISUAL INDICATION OF A DEVICE CONNECTION SPEED
App. No. 11/872,499
→
TEMPERATURE SENSOR WITH DIGITAL BANDGAP
App. No. 11/865,672
→
OUTPUT BUFFER CIRCUIT
App. No. 11/904,901
→
DEVICES AND METHODS FOR SHARING COMMON TARGET DEVICE WITH TWO DIFFERENT HOSTS ACCORDING TO COMMON COMMUNICATION PROTOCOL
App. No. 11/904,758
→
NON-VOLATILE MEMORY SUB-SYSTEM INTEGRATED WITH SECURITY FOR STORING NEAR FIELD TRANSACTIONS
App. No. 11/614,257
→
ELECTRONIC DEVICE INCORPORATING SYSTEM POWER SUPPLY UNIT AND METHOD FOR SUPPLYING POWER SUPPLY VOLTAGE
App. No. 11/512,334
→
CIRCUIT, SYSTEM, AND METHOD FOR MULTIPLEXING SIGNALS WITH REDUCED JITTER
App. No. 11/468,195
→
CIRCUIT FOR ASYNCHRONOUSLY RESETTING SYNCHRONOUS CIRCUIT
App. No. 11/443,110
→
METHOD FOR IMPROVING PERFORMANCE IN A MOBILE DEVICE
App. No. 11/414,845
→
EXTENDING THE DYNAMIC RANGE IN AN ENERGY MEASUREMENT DEVICE
App. No. 11/139,346
→
SIGNAL DETECTION METHOD, FREQUENCY DETECTION METHOD, POWER CONSUMPTION CONTROL METHOD, SIGNAL DETECTING DEVICE, FREQUENCY DETECTING DEVICE, POWER CONSUMPTION CONTROL DEVICE AND ELECTRONIC APPARATUS
App. No. 11/122,123
→
UNIVERSAL SERIAL BUS INTERFACE TO MASS STORAGE DEVICE USING SPECULATIVE WRITE COMMANDS
App. No. 11/038,903
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METHOD AND DEVICE TO IMPROVE USB FLASH WRITE PERFORMANCE
App. No. 10/898,501
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IMPEDANCE MATCHING CIRCUIT
App. No. 10/886,228
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UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
App. No. 10/818,112
→
UNIVERSAL SERIAL BUS INTERFACE TO MASS STORAGE DEVICE
App. No. 10/796,872
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UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BIT FLASH MEMORY DEVICES IN BEOL PROCESSING
App. No. 10/358,589
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METHOD AND DEVICE FOR GENERATING FREQUENCY ADJUSTMENT PARAMETERS FOR A VOLTAGE CONTROLLED OSCILLATOR
App. No. 10/356,449
→
DIGITAL CONFIGURABLE MACRO ARCHITECTURE
App. No. 10/272,231
→
METHOD AND APPARATUS FOR CONFIGURING AN INTERFACE CONTROLLER
App. No. 10/196,106
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SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE USING CONFIGRUATION RESIDING ON THE PERIPHERAL DEVICE BY ELECTRONICALLY SIMULATING A PHYSICAL DISCONNECTION AND RECONNECTION TO A HOST DEVICE
App. No. 10/197,152
→
SERVO CONTROLLER AND SERVO CONTROL METHOD
App. No. 10/187,944
→
ENABLING MULTIPLE ATA DEVICES USING A SINGLE BUS BRIDGE
App. No. 10/186,910
→
CONFIGURABLE USB INTERFACE WITH VIRTUAL REGISTER ARCHITECTURE
App. No. 10/186,465
→
ATA DEVICE ACCESS SYSTEM WITH SURROGATE REGISTERS CORRESPONDING TO ATA REGISTERS
App. No. 10/177,818
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AMPLIFIER CIRCUIT AND METHOD
App. No. 10/146,524
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METHOD AND APPARATUS FOR LOCAL AND GLOBAL POWER MANAGEMENT IN A PROGRAMMABLE ANALOG CIRCUIT
App. No. 09/935,454
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APPARATUS FOR OPTICALLY ISOLATING A USB PERIPHERAL FROM A USB HOST
App. No. 09/935,017
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ARCHITECTURE THAT CONVERTS A HALF-DUPLEX BUS TO A FULL-DUPLEX BUS WHILE KEEPING THE BANDWIDTH OF THE BUS CONSTANT
App. No. 09/915,794
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LOAD/STORE MICROPACKET HANDLING SYSTEM
App. No. 09/915,109
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DEMAND USABLE ADAPTER MEMORY ACCESS MANAGEMENT
App. No. 09/912,954
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RESOURCE LOCKING AND THREAD SYNCHRONIZATION IN A MULTIPROCESSOR ENVIRONMENT
App. No. 09/912,870
→
METHODS AND SYSTEMS FOR A SHARED MEMORY UNIT WITH EXTENDABLE FUNCTIONS
App. No. 09/912,898
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MULTIPLE BLOCK SEQUENTIAL MEMORY MANAGEMENT
App. No. 09/912,834
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DIGITAL CONFIGURABLE MACRO ARCHITECTURE
App. No. 09/909,045
→
ARCHITECTURE OF A PLL WITH DYNAMIC FREQUENCY CONTROL ON A PLD
App. No. 09/893,161
→
MULTIPLE USE OF MICROCONTROLLER PAD
App. No. 09/893,050
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NOVEL POWER ON RESET CIRCUIT FOR A MICROCONTROLLER
App. No. 09/887,955
→
BURIED LAYER SUBSTRATE ISOLATION IN INTEGRATED CIRCUITS
App. No. 09/849,047
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INTELLIGENT, EXTENSIBLE SIE PERIPHERAL DEVICE
App. No. 09/823,414
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SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A UNIVERSAL SERIAL BUS DEVICE
App. No. 09/821,006
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UNIVERSAL SERIAL BUS PERIPHERAL BRIDGE WITH SEQUENCER
App. No. 09/812,475
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SERVO CONTROLLER AND SERVO CONTROL METHOD
App. No. 09/782,297
→