Method and system for providing contact to a first polysilicon layer in a flash memory device
View Patent ↗A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.
1. A method for forming a flash memory device, comprising:
forming a gate stack on a substrate that at least partially overlaps a source region and a drain region of the substrate, the gate stack including a first polysilicon layer;
forming a component on the substrate that does not overlap the source region or the drain region of the substrate, the component including a second polysilicon layer different from the first polysilicon layer;
forming a first silicide layer over the first polysilicon layer;
forming a second silicide layer over the second polysilicon layer;
etching, using the first silicide layer as an etch-stop layer, a first contact hole over the gate stack immediately above the first silicide layer; and
etching, using the second silicide layer as an etch-stop layer, a second contact hole over the component immediately above the second silicide layer.
2. The method of claim 1 , wherein the first silicide layer and the second silicide layer are formed substantially simultaneously.
3. The method of claim 1 , wherein the first silicide layer and the second silicide layer are formed using a self-aligned silicide process.
4. The method of claim 1 , further comprising etching a third contact hole over one of the source region or the drain region immediate above the source region or the drain region.
5. The method of claim 4 , wherein the first contact hole, the second contact hole, and the third contact hole are etched substantially simultaneously.
6. The method of claim 1 , further comprising:
forming a third silicide layer over one of the source region or the drain region; and
etching, using the third silicide layer as an etch-stop layer, a third contact hole over the source region or the drain region immediately above the third silicide layer.
7. The method of claim 1 , further comprising forming spacers on opposite edges of the gate stack prior to forming the first silicide layer and the second silicide layer.
8. The method of claim 1 , wherein:
the gate stack comprises a first combination of layers; and
the component comprises a second combination of layers that is different from the first combination of layers.
9. The method of claim 8 , wherein each of the layers of the second combination of layers are also included within the first combination of layers.