Booster circuit and semiconductor memory
A booster circuit includes a first capacitor and a second capacitor serially coupled between a first node and a second node through a third node; a third capacitor and a fourth capacitor serially coupled between a fourth node and a fifth node through a sixth node; a first switch coupling the third node with a power supply line when the fourth node is set to a first level; a second switch coupling the sixth node with the power supply line when the first node is set to the first level; a third switch transferring a plurality of electric charges of the sixth node to the second node; a fourth switch transferring a plurality of electric charges of the third node to the fifth node; a fifth switch coupling the second node with a voltage line; and a sixth switch coupling the fifth node with the voltage line.
1. A booster circuit comprising:
a first capacitor and a second capacitor serially coupled between a first node and a second node through a third node;
a third capacitor and a fourth capacitor serially coupled between a fourth node and a fifth node through a sixth node;
a first switch that couples the third node with a power supply line when the fourth node is set to a first level;
a second switch that couples the sixth node with the power supply line when the first node is set to the first level;
a third switch that transfers a plurality of electric charges of the sixth node to the second node;
a fourth switch that transfers a plurality of electric charges of the third node to the fifth node;
a fifth switch that couples the second node with a voltage line; and
a sixth switch that couples the fifth node with the voltage line.
2. The booster circuit according to claim 1 , further comprising:
a booster control circuit that alternately sets the first node and the fourth node to the first level, and turns on the fourth switch and the fifth switch while the first node is set to the first level, and turns on the third switch and the sixth switch while the fourth node is set to the first level.
3. The booster circuit according to claim 1 , wherein
the first switch includes a first transistor with a gate coupled to the sixth node, a source coupled to the third node, and a drain coupled to the power supply line; and
the second switch includes a second transistor with a gate coupled to the third node, a source coupled to the sixth node, and a drain coupled to the power supply line.
4. The booster circuit according to claim 1 , wherein
the third switch includes a third transistor with a gate coupled to a seventh node, a source coupled to the second node, and a drain coupled to the sixth node;
the fourth switch includes a fourth transistor with a gate coupled to an eighth node, a source coupled to the fifth node, and a drain coupled to the third node;
an amplitude of a voltage of the seventh node that is applied to the gate of the third transistor in order to turn on/off the third switch is larger than an amplitude of a voltage applied to the first node; and
an amplitude of a voltage of the eighth node that is applied to the gate of the fourth transistor in order to turn on/off the fourth switch is larger than an amplitude of a voltage applied to the fourth node.
5. The booster circuit according to claim 1 , wherein
the fifth switch includes a fifth transistor with a gate coupled to an eighth node, a source coupled to the voltage line, and a drain coupled to the second node;
the sixth switch includes a sixth transistor with a gate coupled to a seventh node, a source coupled to the voltage line, and a drain coupled to the fifth node;
an amplitude of a voltage of the eighth node that is applied to a gate of the fifth transistor in order to turn on/off the fifth switch is larger than an amplitude of a voltage applied to the first node; and
an amplitude of a voltage of the seventh node that is applied to a gate of the sixth transistor in order to turn on/off the sixth switch is larger than an amplitude of a voltage applied to the second node.
6. A semiconductor memory comprising:
a booster circuit includes:
a first capacitor and a second capacitor serially coupled between a first node and a second node through a third node;
a third capacitor and a fourth capacitor serially coupled between a fourth node and a fifth node through a sixth node;
a first switch that couples the third node with a power supply line when the fourth node is set to a first level;
a second switch that couples the sixth node with the power supply line when the first node is set to a first level;
a third switch that transfers a plurality of electric charges of the sixth node to the second node;
a fourth switch that transfers a plurality of electric charges of the third node to the fifth node;
a fifth switch that couples the second node with a voltage line; and
a sixth switch that couples the fifth node to the voltage line;
a booster control circuit configured to alternately set the first node and the fourth node to the first level and turns on the fourth switch and the fifth switch while the first node is set to the first level and turns on the third switch and the sixth switch while the fourth node is set to the first level; and
a memory cell that includes a control gate, wherein a voltage supplied to the control gate is generated by using a voltage that is generated by the booster circuit to the voltage line.
7. The semiconductor memory according to claim 6 , wherein
the memory cell is a nonvolatile memory cell that includes a floating gate laminated over a semiconductor substrate through a first insulating film and a control gate laminated over the floating gate through the second insulating film;
each of the first capacitor and the third capacitor is formed by using the first insulating film as a capacitance film; and
each of the second capacitor and the fourth capacitor is formed by using the second insulating film as a capacitance film.
8. The semiconductor memory according to claim 6 , wherein
withstanding voltages of the first capacitor and the third capacitor are higher than withstanding voltages of the second capacitor and the fourth capacitor.
9. The semiconductor memory according to claim 6 , wherein
the first switch includes a first transistor with a gate coupled to the sixth node, a source coupled to the third node, and a drain coupled to the power supply line; and
the second switch includes a second transistor with a gate coupled to the third node, a source coupled to the sixth node, and a drain coupled to the power supply line.
10. The semiconductor memory according to claim 6 , wherein
the third switch includes a third transistor with a gate coupled to a seventh node, a source coupled to the second node, and a drain coupled to the sixth node;
the fourth switch includes a fourth transistor with a gate coupled to an eighth node, a source coupled to the fifth node, and a drain coupled to the third node;
an amplitude of a voltage of the seventh node that is applied to the gate of the third transistor in order to turn on/off the third switch is larger than an amplitude of a voltage applied to the first node; and
an amplitude of a voltage of the eighth node that is applied to the gate of the fourth transistor in order to turn on/off the fourth switch is larger than an amplitude of a voltage applied to the fourth node.
11. The semiconductor memory according to claim 6 , wherein
the fifth switch includes a fifth transistor with a gate coupled to an eighth node and a source coupled to the voltage line, and a drain coupled to the second node;
the sixth switch includes a sixth transistor with a gate coupled to the seventh node, a source coupled to the voltage line, and a drain coupled to the fifth node;
an amplitude of a voltage of the eighth node that is applied to the gate of the fifth transistor in order to turn on/off the fifth switch is larger than an amplitude of a voltage applied to the first node; and
an amplitude of a voltage of the seventh node that is applied to the gate of the sixth transistor in order to turn on/off the sixth switch is larger than an amplitude of a voltage applied to the second node.