Flash memory and operating system kernel
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.
1. An operating system, comprising:
a page table that stores virtual addresses and physical memory addresses;
a processor that executes a virtual management component that maps the virtual addresses to the physical memory addresses that correspond to at least one FLASH memory device and at least one DRAM memory device employed for random access memory applications;
an allocation component that allocates pages to at least one of the FLASH memory device or the DRAM memory device based on a type of page fault, wherein in response to a read major page fault, the allocation component allocates a page in marked with copy on write protection from a main storage device to the FLASH memory device, and wherein in response to a write major page fault, the allocation component allocates a page in from the main storage device to the DRAM memory device, and wherein in response to a minor page fault on an existing physical DRAM page, the virtual management component maps to the existing physical DRAM page; and
a dynamically adjustable buffer component that temporarily stores a plurality of pages while the pages are being written to at least one of the DRAM or the FLASH devices and forwards the plurality of pages to a direct memory access controller in response to a page request during a write operation, wherein a size of the dynamically adjustable buffer component can be increased in response to a determination that the plurality of pages are greater than the size of the dynamically adjustable buffer component.
2. The system of claim 1 , further comprising a component to control program or erase cycles to the FLASH memory devices.
3. The system of claim 1 , further comprising a component to manage a life cycle of the FLASH memory devices.
4. The system of claim 1 , further comprising a component to manage free memory requirements of the FLASH memory devices or the buffer component.
5. The system of claim 1 , the pages are allocated based off of access types that include read or write access.
6. The system of claim 1 , the pages are allocated based on whether or not hits are detected to an existing mapped page.
7. The system of claim 1 , the allocation component allocates a DRAM page for a write reference that is directed to a FLASH page.
8. The system of claim 1 , further comprising an identifier component that can distinguish between DRAM devices and FLASH devices.
9. The system of claim 8 , the identifier determines a memory capacity for the DRAM devices or the FLASH devices.
10. The system of claim 1 , the buffer component is a DRAM device or a static RAM device.
11. The system of claim 10 , the buffer component is adapted to a dynamic data ram (DDR) memory channel.
12. The system of claim 10 , further comprising a free list that is associated with a buffer component or a FLASH memory device.
13. The system of claim 10 , further comprising a memory management unit that is adapted to operate with a FLASH memory in accordance with slower write cycle times.
14. The system of claim 1 , wherein the page request is directed to a virtual address.
15. A method to operate a memory subsystem, comprising:
mapping a plurality of virtual addresses to physical addresses that correspond to at least one FLASH device and at least one DRAM device
distinguishing between the virtual addresses corresponding to a FLASH device and a DRAM device;
allocating a page in marked with copy-on-write protection from a main storage device to the FLASH device in response to a read major page fault;
allocating a page in from the main storage device to the DRAM device in response to a write major page fault;
mapping to an existing physical DRAM page in response to a minor page fault on the existing physical DRAM page;
increasing a size of the at least one DRAM device in response to an analysis that a plurality of pages that corresponds to the page write requests is larger than a current size of the at least one DRAM device; and
employing a processor to forward data while pages are being written to the DRAM device.
16. The method of claim 15 , further comprising moving the data to the FLASH device during background memory operations.
17. The method of claim 15 , further comprising operating a free list for the FLASH device or a random access buffer device.
18. An operating system, comprising:
means for distinguishing between virtual addresses that correspond to a physical location on FLASH devices and a physical location on DRAM devices;
means for allocating a page in marked with copy-on-write protection from a main storage device to the FLASH device in response to a read major page fault;
means for allocating a page in from the main storage device to the DRAM device in response to a write major page fault;
means for mapping to an existing physical DRAM page in response to a minor page fault on the existing physical DRAM page;
means for increasing a size of the DRAM devices in response to an analysis that a plurality of pages that corresponds to the page write requests are larger than a current size of the DRAM devices;
means for buffering a portion of data to facilitate controlling write access to the DRAM device; and
means for employing a processor to forward data while pages are being written to the DRAM device.