Nonvolatile memory device and method to control the same

1. A nonvolatile memory device comprising:

a source selector transistor connected at one end to a source line;

a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor; and

a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being connected at one end to the drain terminal of said cell selector transistor and at the other end to the bit line,

wherein said source selector transistor and said cell selector transistor which are provided between one end of said variable resistor element to be accessed and said source line are controlled to turn on.

2. The nonvolatile memory device according to claim 1 , wherein the word line to the gate terminal of said cell selector transistor and said bit line are disposed to run parallel to each other.

3. The nonvolatile memory device according to claim 1 , wherein said source selector transistor is connected to both ends of said plurality of cell selector transistors which are connected in series in said basic memory unit.

4. The nonvolatile memory device according to claim 3 , wherein a switch which connects said basic memory units with each other is disposed substantially at the center of said plurality of cell selector transistors that are connected in series.

5. The nonvolatile memory device according to claim 3 , wherein said basic memory units which are connected serially are disposed in mirror arrangement substantially at the center of said plurality of cell selector transistors that are connected in series.

6. The nonvolatile memory device according to claim 3 , wherein a path involving smaller number of said cell selector transistors is selected from among two paths running from the variable resistor element to be accessed to said source line, and said cell selector transistor and said source selector transistor which are provided in said path are controlled to turn on.

7. The nonvolatile memory device according to claim 3 , wherein all of said cell selector transistors and said source selector transistor provided in the two paths running from the variable resistor element to be accessed to said source line are controlled to turn on.

8. The nonvolatile memory device according to claim 1 , wherein said basic memory units are provided in plurality to form a memory block, gate terminals of said cell selector transistors disposed at a corresponding position in each of said basic memory units are connected to a common word line in said memory block, and the other end of said variable resistor element disposed at a corresponding position in each of said basic memory units is connected to a common bit line in said memory block.

9. A memory system comprising:

a control circuit;

a source line decoder coupled to said control circuit;

a column decoder coupled to said source line decoder; and

a memory cell array coupled to said control circuit, wherein said memory array comprises a nonvolatile memory device comprising:

a source selector transistor connected at one end thereof to a source line;

a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor; and

a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being connected at one end thereof to the drain terminal of said cell selector transistor and connected at the other end thereof to the bit line,

wherein said source selector transistor and said cell selector transistor which are provided between one end of said variable resistor element to be accessed and said source line are controlled to turn on.

10. The memory system according to claim 9 , wherein the word line to the gate terminal of said cell selector transistor and said bit line are disposed to run parallel to each other.

11. The memory system according to claim 9 , wherein said source selector transistor is connected to both ends of said plurality of cell selector transistors which are connected in series in said basic memory unit.

12. The memory system according to claim 11 , wherein a switch which connects said basic memory units with each other is disposed substantially at the center of said plurality of cell selector transistors that are connected in series.

13. The memory system according to claim 11 , wherein said basic memory units which are connected successively are disposed in mirror arrangement substantially at the center of said plurality of cell selector transistors that are connected in series.

14. The memory system according to claim 11 , wherein a path involving smaller number of said cell selector transistors is selected from among two paths running from the variable resistor element to be accessed to said source line, and said cell selector transistor and said source selector transistor provided in said path are controlled to turn on.

15. The memory system according to claim 11 , wherein all of said cell selector transistors and said source selector transistor provided in the two paths running from the variable resistor element to be accessed to said source line are controlled to turn on.

16. The memory system according to claim 9 , wherein said basic memory units are provided in plurality to form a memory block, gate terminals of said cell selector transistors disposed at a corresponding position in each of said basic memory units are connected to a common word line in said memory block, and the other end of said variable resistor element disposed at a corresponding position in each of said basic memory units is connected to a common bit line in said memory block.

17. The memory system according to claim 9 , wherein said control circuit receives control signal, address signal and data inputs and controls said column decoder and said source line decoder.

18. A method for controlling a nonvolatile memory device comprising a source selector transistor connected at one end thereof to a source line, a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor, and variable resistor element which is a memory element to store bit information provided for each of said cell selector transistors and is connected at one end thereof to the drain terminal of said cell selector transistor and connected at the other end thereof to the bit line, said method comprising the steps of:

causing said source selector transistor and said cell selector transistor, which are provided between one end of said variable resistor element to be accessed and said source line, to turn on; and

biasing a voltage stress between said bit line, to which said variable resistor element to be accessed and said source line is connected, and said source line.

19. The method for controlling the nonvolatile memory device according to claim 18 , wherein in case said source selector transistor is connected to both ends of said plurality of cell selector transistors which are connected in series with each other, said source selector transistor and said cell selector transistor located on a path involving a smaller number of said cell selector transistors, among two paths running from said variable resistor element to be accessed to said source line, are turned on.

20. The method for controlling the nonvolatile memory device according to claim 18 , wherein in case said source selector transistor is connected to both ends of said plurality of cell selector transistors which are connected in series with each other, all of said source selector transistors and said cell selector transistors, which are located on the two paths from said variable resistor element to be accessed to said source line, are turned on.