IP Library Granted Patent US 8,438,460
Granted Patent B2
US 8,438,460 · App. 13/531,282 · Granted May 7, 2013

Error correction scheme for non-volatile memory

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Quick Facts
Patent No.
US 8,438,460
App. No.
13/531,282
Granted
May 7, 2013
Kind
B2
Abstract

Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level

Claims (18)

1. A non-volatile memory system, comprising:

a data area for storing initial data;

a buffer for storing the initial data and additional data, wherein the additional data is programmed in the data area subsequent to the initial data;

an error correcting code generation circuit for generating an error correcting code for the initial data and the additional data in response to receipt of a code generation command; and

an error correcting code (ECC) area for storing the error correcting code.

2. The non-volatile memory system according to claim 1 , wherein the error correcting code generation circuit is inactive until the receipt of the code generation command.

3. The non-volatile memory system according to claim 1 , wherein the receipt of the code generation command is performed when a combined size of the initial data and the additional data is approximately equal to a size of the data area.

4. The non-volatile memory system according to claim 1 , wherein the initial data and the additional data are corrected based on the error correcting code when the initial data and the additional data are processed for reading.

5. The non-volatile memory system according to claim 1 , wherein the data area comprises a memory sector.

6. A method for a non-volatile memory system with a data area programmed with initial data, comprising:

receiving a code generation command from a memory controller;

generating an error correcting code when additional data is programmed subsequent to the receiving of the code generation command,

wherein the error correcting code is associated with the initial data and the additional data; and

storing the error correcting code in an error correcting code area associated with the data area.

7. The method according to claim 6 , wherein the generating of the error correcting code comprises processing the initial data and the additional data using a buffer.

8. The method according to claim 6 , wherein the collection of data based on the error correcting code when the initial data and the additional data are processed for reading.

9. The method according to claim 6 , wherein the data area comprises a memory sector.

10. The method according to claim 6 , wherein the initial data is a combination of a plurality of programming sessions performed prior to the receiving the code generation command.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036055/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2015
From: KASA, YASUSHI
To: SPANSION LLC
Reel/Frame 034721/0278 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →