IP Library Granted Patent US 8,107,487
Granted Patent B2
US 8,107,487 · App. 12/434,415 · Granted Jan 31, 2012

Packet communication device for communicating packet to be transferred through packet communication which is time-managed in constant cycle and packet communication method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,107,487
App. No.
12/434,415
Granted
Jan 31, 2012
Kind
B2
Abstract

A packet communication device for communicating a packet to be transferred in constant cycle, comprising one of a logic inversion section configured to invert a logical value with respect to at least one bit included in a first string of bits included in a first packet; and a register section configured to store another string of bits having a logical value different from a given logical value of the first string of bits; and a selector section configured to select one of the first string of bits and a second string of bits that is output from one of the logic inversion section and the register section to designate any one of a plurality of devices, wherein the packet communication is performed when a selected string of bits selected by the selector section conforms to a setting value of a receiving side.

Claims (16)

1. A packet communication device for switching a packet to be transferred in packet communication which is time-managed in constant cycles, the packet communication device comprising:

a changing section configured to change a portion of a first packet to be transmitted in each of the constant cycles,

wherein:

the time-managed packet communication represents isochronous transfers as supported based on IEEE 1394 standard;

configuration of the first packet is compliant with the IEEE 1394 standard;

the changing section represents a redundant bit changing section for changing redundant bits in the first packet;

the packet communication device further comprises a plurality of packet transmitting devices;

a transmitting device configured to transmit a packet next is designated from amongst the plurality of transmitting devices, based on a state of the portion of the first packet to be transmitted to the plurality of packet transmitting devices, in each of the constant cycles;

both a transmitting device and a receiving device for second packets which are transferred isochronously have the redundant bit changing section;

at least either one of the transmitting devices and the receiving device comprises:

a selector configured to select transaction labels of the first packet; and

a switching register coupled to the selector; and

the transmitting device and the receiving device comprise:

a status storing register configured to store status information of an input device; and

an MPU coupled to the status storing register;

wherein the redundant bit changing section and the switching register are controlled by the MPU.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2009
From: TAKI, NOBUHIRO
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 022642/0824 →