Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory

1. A method of erasing memory cells in a memory device, comprising:

supplying a predetermined voltage potential to each memory cell of a subset of memory cells in the memory device at substantially the same time, the subset of memory cells determined based in part on a relative location of a respective memory cell to other memory cells in the memory device;

moving stored charge from each memory cell of the subset of memory cells to facilitate erasing the subset of memory cells;

selecting at least one subset of memory cells based in part on the relative location of a respective memory cell to other memory cells in the memory device such that each memory cell of the at least one subset of memory cells has at least one neighbor memory cell that is adjacent to such memory cell and is in the at least one subset of memory cells; and

erasing each memory cell of the at least one subset of memory cells at substantially the same time.

2. The method of claim 1 , further comprising:

evaluating the respective locations of each memory cell in a sector of the memory device; and

determining the at least one subset of memory cells such that a maximum number of memory cells in the at least one subset of memory cells has two neighbor memory cells adjacent to such memory cell that are in the at least one subset of memory cells.

3. The method of claim 1 , wherein supplying the predetermined voltage potential to each memory cell of a subset of memory cells in the memory device at substantially the same time, further comprising:

supplying a predetermined negative voltage level to word lines respectively associated with each memory cell of the subset of memory cells; and

supplying a predetermined positive voltage level to a substrate associated with the subset of memory cells.

4. The method of claim 3 , further comprising:

generating an erase command; and

erasing the subset of memory cells via a Fowler-Nordheim channel erase.

5. The method of claim 1 , further comprising:

at least one of:

selecting at least one memory cell to be in the subset of memory cells based in part on the at least one memory cell having two neighbor memory cells adjacent to the at least one memory cell that are in the subset of memory cells, where the at least one memory cell is not at the end of a row of memory cells associated with a sector in a memory array of the memory device, or

selecting at least one memory cell to be in the subset of memory cells based in part on the at least one memory cell having one neighbor memory cell adjacent to the at least one memory cell that is in the subset of memory cells, where the at least one memory cell is at the end of a row of memory cells associated with a sector in a memory array of the memory device, or a combination thereof.

6. The method of claim 1 , further comprising:

erasing the subset of memory cells at substantially the same time, wherein the subset of memory cells includes a number of memory cells that is less than the number of memory cells in a sector in a memory array of the memory device; and

erasing at least one other subset of memory cells at substantially the same time, wherein the at least one other subset of memory cells is located in the same sector as the subset of memory cells.

7. The method of claim 1 , further comprising:

generating an erase command; and

erasing the subset of memory cells via a Fowler-Nordheim channel erase.

8. A method of erasing memory cells in a memory device, comprising:

supplying a predetermined voltage potential to at least one memory cell of a subset of memory cells in the memory device, the subset of memory cells determined based at least in part on a relative location of the at least one memory cell to other memory cells in the memory device;

supplying a predetermined voltage bias, which corresponds to the predetermined voltage potential, to at least a first neighbor memory cell and a second neighbor memory cell of the subset of memory cells at substantially a same time as the predetermined voltage potential is supplied to the at least one memory cell, the at least one memory cell is associated with a word line, the first neighbor memory cell is associated with a first neighbor word line adjacent to the word line, and the second neighbor memory cell is associated with a second neighbor word line adjacent to the word line; and

moving stored charge from the at least one memory cell of the subset of memory cells in response to the supplying of the predetermined voltage potential to facilitate erasing at least the at least one memory cell.

9. The method of claim 8 , further comprising:

selecting at least one subset of memory cells based at least in part on relative location of a respective memory cell to other memory cells in the memory device such that each memory cell of the at least one subset of memory cells has at least one neighbor memory cell that is adjacent to the respective memory cell and is in the at least one subset of memory cells;

erasing at least the respective memory cell of the at least one subset of memory cells at substantially the same time in response to supplying of the predetermined voltage potential; and

supplying the predetermined voltage bias, which corresponds to the predetermined voltage potential, to the at least one neighbor memory cell at substantially a same time as the predetermined voltage potential is supplied to the at least the respective memory cell, the at least the respective memory cell is associated with a respective word line, the at least one neighbor memory cell is associated with at least one neighbor word line adjacent to the respective word line.

10. The method of claim 8 , further comprising:

evaluating the respective locations of at least the at least one memory cell, the first neighbor memory cell and the second neighbor memory cell in a sector of the memory device; and

determining the subset of memory cells such that a maximum number of memory cells in the subset of memory cells has two neighbor memory cells adjacent to such memory cell that are in the subset of memory cells.

11. The method of claim 8 , wherein the supplying the predetermined voltage bias, further comprising:

supplying a predetermined negative voltage level to at least the first neighbor word line and the second neighbor word line respectively associated with at least the first neighbor memory cell and the second neighbor memory cell of the subset of memory cells; and

supplying a predetermined positive voltage level to a substrate associated with the subset of memory cells.

12. The method of claim 8 , further comprising:

selecting at least one other memory cell to be in the subset of memory cells based at least in part on the at least one other memory cell having one neighbor memory cell adjacent to the at least one other memory cell that is in the subset of memory cells, where the at least one other memory cell is at the end of a row of memory cells associated with a sector in a memory array of the memory device.

13. The method of claim 8 , further comprising:

erasing the subset of memory cells at substantially the same time, wherein the subset of memory cells includes a specified number of memory cells that is less than a number of memory cells in a sector in a memory array of the memory device; and

erasing at least one other subset of memory cells at substantially the same time, wherein the at least one other subset of memory cells is located in the same sector as the subset of memory cells.

14. The method of claim 8 , further comprising:

generating an erase command; and

erasing the subset of memory cells via a Fowler-Nordheim channel erase.

15. A method of erasing memory cells in a memory device comprised in a cellular phone, comprising:

supplying a predetermined voltage potential to at least one memory cell of a subset of memory cells in the memory device, the subset of memory cells determined based at least in part on a relative location of the at least one memory cell to other memory cells in the memory device;

supplying a predetermined voltage bias, which corresponds to the predetermined voltage potential, to at least a first neighbor memory cell and a second neighbor memory cell of the subset of memory cells at substantially a same time as the predetermined voltage potential is supplied to the at least one memory cell, the at least one memory cell is associated with a word line, the first neighbor memory cell is associated with a first neighbor word line adjacent to the word line, and the second neighbor memory cell is associated with a second neighbor word line adjacent to the word line; and

moving stored charge from the at least one memory cell of the subset of memory cells in response to the supplying of the predetermined voltage potential to facilitate erasing at least the at least one memory cell.

16. The method of claim 15 , further comprising:

selecting at least one subset of memory cells based at least in part on relative location of a respective memory cell to other memory cells in the memory device such that each memory cell of the at least one subset of memory cells has at least one neighbor memory cell that is adjacent to the respective memory cell and is in the at least one subset of memory cells;

erasing at least the respective memory cell of the at least one subset of memory cells at substantially the same time in response to supplying of the predetermined voltage potential; and

supplying the predetermined voltage bias, which corresponds to the predetermined voltage potential, to the at least one neighbor memory cell at substantially a same time as the predetermined voltage potential is supplied to the at least the respective memory cell, the at least the respective memory cell is associated with a respective word line, the at least one neighbor memory cell is associated with at least one neighbor word line adjacent to the respective word line.

17. The method of claim 15 , further comprising:

evaluating the respective locations of at least the at least one memory cell, the first neighbor memory cell and the second neighbor memory cell in a sector of the memory device; and

determining the subset of memory cells such that a maximum number of memory cells in the subset of memory cells has two neighbor memory cells adjacent to such memory cell that are in the subset of memory cells.

18. The method of claim 15 , wherein the supplying the predetermined voltage bias, further comprising:

supplying a predetermined negative voltage level to at least the first neighbor word line and the second neighbor word line respectively associated with at least the first neighbor memory cell and the second neighbor memory cell of the subset of memory cells; and

supplying a predetermined positive voltage level to a substrate associated with the subset of memory cells.

19. The method of claim 15 , further comprising:

selecting at least one other memory cell to be in the subset of memory cells based at least in part on the at least one other memory cell having one neighbor memory cell adjacent to the at least one other memory cell that is in the subset of memory cells, where the at least one other memory cell is at the end of a row of memory cells associated with a sector in a memory array of the memory device.

20. The method of claim 15 , further comprising:

erasing the subset of memory cells at substantially the same time, wherein the subset of memory cells includes a specified number of memory cells that is less than a number of memory cells in a sector in a memory array of the memory device; and erasing at least one other subset of memory cells at substantially the same time, wherein the at least one other subset of memory cells is located in the same sector as the subset of memory cells.