A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.
1. A phase locked loop (PLL) circuit, comprising:
a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal;
an oscillator for outputting an output signal having a frequency in accordance with an output of the phase comparator;
a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal;
a delay circuit for controlling a delay time of the output signal of the oscillator according to a phase difference between the reference signal and the feedback signal,
wherein the delay circuit is provided outside the feedback loop; and
a voltage/current converter for converting a voltage in accordance with an output of the phase comparator;
wherein the oscillator is a current controlled oscillator that includes differential amplifiers coupled to one another in a ring shape,
wherein an output current of the voltage/current converter is supplied as a bias current to the differential amplifiers included in the current controlled oscillator, and
wherein the delay circuit includes a differential amplifier having a same configuration as the differential amplifiers of the current controlled oscillator.
2. The PLL circuit according to claim 1 , wherein the output signal of the current controlled oscillator is output to a load circuit via the delay circuit.
3. The PLL circuit according to claim 1 , wherein the delay circuit controls the delay time so as to keep a given rate relative to a cycle of the output signal of the oscillator.
4. The PLL circuit according to claim 1 , wherein the delay circuit controls the delay time to decrease when the frequency increases.
5. The PLL circuit according to claim 1 , wherein the delay circuit controls the delay time to increase when the frequency decreases.