IP Library Granted Patent US 8,824,469
Granted Patent B2
US 8,824,469 · App. 13/313,565 · Granted Sep 2, 2014

Packet communication device for communicating packet to be transferred through packet communication which is time-managed in constant cycle and packet communication method thereof

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Quick Facts
Patent No.
US 8,824,469
App. No.
13/313,565
Granted
Sep 2, 2014
Kind
B2
Abstract

A packet communication device for communicating a packet to be transferred in constant cycle, comprising one of a logic inversion section configured to invert a logical value with respect to at least one bit included in a first string of bits included in a first packet; and a register section configured to store another string of bits having a logical value different from a given logical value of the first string of bits; and a selector section configured to select one of the first string of bits and a second string of bits that is output from one of the logic inversion section and the register section to designate any one of a plurality of devices, wherein the packet communication is performed when a selected string of bits selected by the selector section conforms to a setting value of a receiving side.

Claims (38)

1. A packet communication device that is provided at a receiving side and receives a packet from another packet communication device provided at a transmitting side through packet communication which is time-managed in constant cycle, the packet communication device comprising:

a logic inverter circuit configured to invert a logical value with respect to at least one bit included in a first string of bits having a given logical value and being included in a first packet to be transferred from the transmitting side;

a first selector circuit configured to select either one of the first string of bits and a second string of bits in which the at least one bit of the first string of bits is replaced with at least one bit output from the logic inverter circuit, wherein the packet communication is performed when a value of a selected string of bits which is selected by the first selector circuit provided at the receiving side conforms to a value of a string of bits which are set at the transmitting side;

a register circuit configured to store a plurality of third strings of bits, the plurality of third strings of bits having different logical values from each other; and

a second selector circuit configured to select either one of the plurality of third strings of bits, wherein the packet communication is performed when a value of one of the plurality of third strings of bits which is selected by the second selector circuit provided at the receiving side conforms to a value of a string of bits which are included in the first packet transferred from the transmitting side.

2. The packet communication device according to claim 1 , wherein:

the time-managed packet communication represents isochronous transfers as supported based on IEEE 1394 standard;

configuration of the first packet is compliant with the IEEE 1394 standard; and

the first string of bits included in the first packet represents CRC data.

3. The packet communication device according to claim 1 , wherein:

the time-managed packet communication represents isochronous transfers as supported based on IEEE 1394 standard;

configuration of the first packet is compliant with the IEEE 1394 standard; and

the first string of bits included in the first packet represents transaction labels.

4. The packet communication device according to claim 1 , wherein:

the time-managed packet communication represents isochronous transfers as supported based on IEEE 1394 standard;

configuration of the first packet is compliant with the IEEE 1394 standard; and

the first string of bits included in the first packet represents CRC data and transaction labels.

5. The packet communication device according to claim 1 , wherein, according to status information transmitted from the packet communication device at the transmitting side, the packet communication device at the receiving side changes the setting value thereof so as to conform to the selected string of bits which is selected by the selector section.

6. A packet communication method that is conducted at a receiving side and receives a packet from a transmitting side through packet communication which is time-managed in constant cycle, a first string of bits having a given logical value and being included in a first packet to be transferred from the transmitting side, the packet communication method comprising:

inverting a logical value with respect to at least one bit included in the first string of bits;

selecting either one of the first string of bits and a second string of bits in which at least one bit of the first string of bits is replaced with at least one bit output from the logic inverter circuit, wherein the packet communication is performed when a value of a selected string of bits which is selected by the selecting conforms to a value of a string of bits which are set at the transmitting side;

storing a plurality of third strings of bits, the plurality of third strings of bits having different logical values from each other; and

selecting either one of the plurality of third strings of bits, wherein the packet communication is performed when a value of one of the plurality of third strings of bits which is selected by the second selector circuit provided at the receiving side conforms to a value of a string of bits which are included in the first packet transferred from the transmitting side.

7. The packet communication method according to claim 6 , wherein:

the time-managed packet communication represents isochronous transfers as supported based on IEEE 1394 standard;

configuration of the first packet is compliant with the IEEE 1394 standard; and

the first string of bits included in the first packet represents CRC data.

8. The packet communication method according to claim 6 , wherein:

the time-managed packet communication represents isochronous transfers as supported based on IEEE 1394 standard;

configuration of the first packet is compliant with the IEEE 1394 standard; and

the first string of bits included in the first packet represents transaction labels.

9. The packet communication method according to claim 6 , wherein:

the time-managed packet communication represents isochronous transfers as supported based on IEEE 1394 standard;

configuration of the first packet is compliant with the IEEE 1394 standard; and

the first string of bits included in the first packet represents CRC data and transaction labels.

10. The packet communication method according to claim 6 , comprising:

receiving status information transmitted from a transmitting side; and

changing the setting value of the receiving side so as to conform to the selected string of bits which is selected by the selecting, according to the receiving of the status information.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
CHANGE OF NAME Recorded Mar 19, 2014
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 032479/0646 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2014
From: TAKI, NOBUHIRO
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 032307/0424 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →