System and method of operation for resistive change memory

1. A semiconductor device comprising:

a data storage element having a variable resistance and an electrode; and

a controller that selects between a first mode that stores data by a resistance value of the variable resistance, and a second mode that stores data by an amount of electrical charge stored in the electrode.

2. The semiconductor device according to claim 1 , wherein

the first mode stores data by changing the variable resistance to either a high resistive state or a low resistive state; and

the second mode stores data by changing the electrode to either a charged state or a discharged state.

3. The semiconductor device according to claim 1 , wherein the controller controls a time during which a voltage is applied to the data storage element when writing data in the first mode to be longer than a time during which a voltage is applied to the data storage element when writing data in the second mode.

4. The semiconductor device according to claim 2 , wherein the controller maintains the variable resistance at the high resistive state when the second mode is selected.

5. The semiconductor device according to claim 4 , wherein when writing data in the second mode, the controller controls the voltage applied to the electrode to be lower than a threshold voltage for changing the variable resistance from the high resistive state to the low resistive state.

6. The semiconductor device according to claim 5 , wherein when writing data in the first mode, the controller applies a voltage higher than the threshold voltage to the data storage element when changing the variable resistance to the low resistive state, and applies a voltage lower than the threshold voltage to the data storage element for a longer time than when changing the variable resistance to the low resistive state when changing the variable resistance to the high resistive state.

7. The semiconductor device according to claim 2 , further comprising:

a select transistor in which either a source or a drain is coupled to the data storage element; wherein

the controller controls a current flowing through the data storage element by controlling a gate voltage of the select transistor, and controls a gate voltage when changing the variable resistance to the low resistive state when writing data in the first mode to be smaller than a gate voltage when changing the variable resistance to the high resistive state when writing data in the first mode and when in the second mode.

8. The semiconductor device according to claim 1 , wherein the controller performs a refresh operation of the data storage element when the second mode is selected.

9. The semiconductor device according to claim 1 , further comprising:

the data storage element including a first data storage element and a second data storage element; and

a plurality of bit lines comprising a first bit line to which the first data storage element is coupled and a second bit line to which the second data storage element is coupled; wherein

the controller sets the first bit line to a high level and the second bit line to a voltage level lower than the high level when writing to the first data storage element, and sets the second bit line to the high level and the first bit line to a voltage level lower than the high level when writing to the second data storage element when writing data in the first mode; and

the controller sets the first bit line to a high level and the second bit line to a low level when writing a logical high to the first data storage element and the second data storage element, and sets the first bit line to the low level and the second bit line to the high level when writing a logical low to the first data storage element and the second data storage element when writing data in the second mode.

10. The semiconductor device according to claim 9 , wherein

the controller applies a voltage for changing the variable resistance to either a high resistive state or a low resistive state to a bit line which is set to a high level among the first bit line and the second bit line when writing data in the first mode; and

the controller applies a voltage for charging electrical charges to the electrode to a bit line which is set to a high level among the first bit line and the second bit line, and applies a voltage for discharging the electrode to a bit line set to a low level when writing data in the second mode.

11. The semiconductor device according to claim 1 , further comprising:

the data storage element including a first data storage element and a second data storage element; and

a pair of bit lines comprising a first bit line to which the first data storage element is coupled and a second bit line to which the second data storage element is coupled; wherein

the controller reads out data by raising the second bit line up to a reference voltage that is referred to when reading data, raising the first bit line to a voltage higher than the reference voltage, conducting the first data storage element and the first bit line, and comparing voltages, after performing the conducting, of the first bit line and the second bit line when reading out data from the first data storage element in the first mode; and

the controller reads out data by raising the first bit line and the second bit line up to the reference voltage, conducting the data storage element and the first bit line, and comparing voltages, after performing the conducting, of the first bit line and the second bit line when reading out data from the first data storage element in the second mode.

12. The semiconductor device according to claim 11 , further comprising:

a detector circuit coupled to the first bit line and the second bit line; wherein

the controller performs a control such that, when reading data in the first mode and the second mode, a potential difference between the first bit line and the second bit line in the detector circuit is amplified.

13. The semiconductor device according to claim 12 , wherein the detector circuit is used in common in the first mode and the second mode.

14. The semiconductor device according to claim 11 , wherein the controller short-circuits, when reading data in the first mode and the second mode, the first bit line and the second bit line after reading data.

15. The semiconductor device according to claim 2 , wherein

the controller selects, in addition to the first mode and the second mode, a third mode that stores data by changing the variable resistance to either a high resistive state or a low resistive state;

a resistance value when the variable resistance is in the high resistive state in the third mode is smaller than a resistance value when the variable resistance is in the high resistive state in the first mode; and

a resistance value when the variable resistance is in the low resistive state in the third mode is larger than a resistance value when the variable resistance is in the low resistive state in the first mode.

16. The semiconductor device according to claim 15 , wherein the controller controls a time during which a voltage is applied to the data storage element when writing data in the third mode to be shorter than a time during which a voltage is applied to the data storage element when writing data in the first mode, and also to be longer than a time during which a voltage is applied to the data storage element when writing data in the second mode.

17. The semiconductor device according to claim 16 , wherein

the controller applies a voltage higher than a threshold voltage for changing the variable resistance from the high resistive state to the low resistive state to the data storage element when changing the variable resistance to the low resistive state when writing data in the third mode, and

the controller applies a voltage lower than the threshold voltage to the data storage element for a longer time than when changing the variable resistance to the low resistive state when changing the variable resistance to the high resistive state.

18. The semiconductor device according to claim 16 , further comprising:

a select transistor in which either a source or a drain is coupled to the data storage element; wherein

the controller controls a current flowing through the data storage element by controlling a gate voltage of the select transistor, and controls a gate voltage when changing the variable resistance to the low resistive state when writing data in the third mode to be smaller than a gate voltage when changing the variable resistance to the high resistive state when writing data in the third mode and when in the second mode.

19. The semiconductor device according to claim 15 , wherein the controller performs a refresh operation of the data storage element at a longer interval than when the second mode is selected when writing data in the third mode.

20. The semiconductor device according to claim 1 , further comprising:

a select register that stores a mode of the data storage element; wherein

the controller selects a mode of the data storage element by referencing a value of the select transistor.

21. The semiconductor device according to claim 1 , further comprising:

a control terminal that inputs a mode of the data storage element to the controller; wherein

the controller selects a mode of the data storage element according to an input from the control terminal.

22. A method for controlling a semiconductor device that includes a data storage element including a variable resistance and an electrode, the method comprising:

selecting a first stage that stores data by changing the variable resistance to either a high resistive state or a low resistive state, and a second stage that stores data by an amount of electrical charges stored in the electrode.

23. The method for controlling a semiconductor device according to claim 22 , wherein

the first stage includes writing data by applying a first voltage to the data storage element;

the second stage includes writing data by applying a second voltage to the data storage element; and

a time during which the first voltage is applied is longer than a time during which the second voltage is applied.

24. The method for controlling a semiconductor device according to claim 22 , wherein the writing of the data to the data storage element in the first stage comprises:

setting a first bit line to a high level and a second bit line to a voltage level lower than the high level when writing to a first data storage element;

setting the second bit line to a high level and the first bit line to a voltage level lower than the high level when writing to a second data storage element.

25. The method for controlling a semiconductor device according to claim 22 , wherein the writing of the data to the data storage element in the second stage comprises:

setting the first bit line to a high level and the second bit line to a low level when writing a logical high to the first data storage element and the second data storage element; and

setting the first bit line to a low level and the second bit line to a high level when writing a logical low to the first data storage element and the second data storage element.

26. The method for controlling a semiconductor device according to claim 22 , wherein the first stage comprises:

raising a second bit line up to a reference voltage that is referred to when reading data;

raising a first bit line to a voltage higher than the reference voltage;

conducting a data storage element and the first bit line; and

reading out data by comparing voltages of the first bit line and the second bit line, wherein reading out data is performed after conducting the data storage element and the first bit line.

27. The method for controlling a semiconductor device according to claim 22 , wherein the second stage comprises:

raising a first bit line and a second bit line up to a reference voltage;

conducting a data storage element and the first bit line; and

reading out data by comparing voltages of the first bit line and the second bit line, wherein reading out data is performed after performing conducting the data storage element and the first bit line.

28. The method for controlling a semiconductor device according to claim 22 , further comprising:

selecting any one of the first stage, the second stage, or a third stage that stores data by changing the variable resistance to either a high resistive state or a low resistive state; wherein

a resistance value when the variable resistance is in the high resistive state in the third stage is smaller than a resistance value when the variable resistance is in the high resistive state in the first stage; and

a resistance value when the variable resistance is in the low resistive state in the third stage is larger than a resistance value when the variable resistance is in the low resistive state in the first stage.

29. The method for controlling a semiconductor device according to claim 28 , wherein the third stage comprises:

writing data by applying a third voltage to the data storage element; wherein

a time during which the third voltage is applied is shorter than a time during which the first voltage is applied and is longer than a time during which the second voltage is applied.