Partial local self-boosting of a memory cell channel

1. A method for partial local self-boosting of a memory cell channel, comprising:

turning off an isolating memory cell located on a source side of a program inhibited memory cell;

using a gating memory cell located on a drain side of said program inhibited memory cell, passing pre-charge voltage to said program inhibited memory cell to provide a pre-charge voltage to a channel of said program inhibited memory cell and passing pre-charge voltage to a buffering memory cell located on said source side of said program inhibited memory cell to provide a pre-charge voltage to a channel of said buffering memory cell;

turning off said gating memory cell that is located on said drain side of said program inhibited memory cell; and

during programming, applying a programming voltage to the gate of said program inhibited memory cell wherein a channel voltage of said program inhibited memory cell is raised beyond a level raised by said pre-charge voltage.

2. The method of claim 1 wherein said turning off said gating memory cell is done by lowering the voltage applied to the gate of said gating memory cell.

3. The method of claim 1 wherein said turning off said gating memory cell is done without lowering the voltage applied to the gate of said gating memory cell.

4. The method of claim 1 wherein turning off said isolating memory cell comprises applying a voltage of zero volts or other turn-off voltage to the gate of said isolating memory cell.

5. The method of claim 1 further comprising applying a predetermined voltage to the gate of said buffering memory cell located adjacent to said program inhibited memory cell on the source side of said program inhibited memory cell.

6. The method of claim 1 wherein different voltages are applied to the gates of memory cells located on the drain side of said program inhibited memory cell.

7. The method of claim 1 wherein said gating memory cell is selected to control leakage current.

8. The method of claim 1 wherein said gating memory cell is selected from among a plurality of memory cells that are located on the drain side of said program inhibited memory cell.

9. A method of programming a NAND memory cell, comprising:

identifying a memory cell to be programmed;

passing pre-charge voltage to a program inhibited memory cell associated with said memory cell to be programmed to provide a pre-charge voltage to the channel of said program inhibited memory cell;

turning off a gating memory cell that is located on the drain side of said program inhibited memory cell;

applying a program voltage to the gate of said memory cell to be programmed and to the gate of said program inhibited memory cell wherein a channel voltage of said program inhibited memory cell is raised above the voltage level to which it is raised by said pre-charge voltage; and

storing a value in said memory cell to be programmed.

10. The method of claim 9 wherein said turning off said gating memory cell is done by lowering the voltage applied to the gate of said gating memory cell.

11. The method of claim 9 wherein said turning off said gating memory cell is done without lowering the voltage applied to the gate of said gating memory cell.

12. The method of claim 9 wherein turning off said isolating memory cell comprises applying a voltage of zero volts or other turn-off voltage to the gate of said isolating memory cell.

13. The method of claim 9 further comprising applying a predetermined voltage to the gate of said buffering memory cell located adjacent to said program inhibited memory cell on the source side of said program inhibited memory cell.

14. The method of claim 9 wherein different voltages are applied to the gates of memory cells located on the drain side of said program inhibited memory cell.

15. The method of claim 9 wherein said gating memory cell is selected to control leakage current.

16. The method of claim 9 wherein said gating memory cell is selected from among a plurality of memory cells that are located on the drain side of said program inhibited memory cell.

17. In a NAND memory cell array comprising a plurality of NAND memory cell strings, a method for programming a memory cell, comprising:

selecting a word line that is associated with a memory cell of said NAND memory cell array to be programmed and at least one program inhibited memory cell;

turning off an isolating memory cell located on a source side of said at least one program inhibited memory cell;

using a gating memory cell located on a drain side of said at least one program inhibited memory cell, passing pre-charge voltage to said at least one program inhibited memory cell to provide a pre-charge voltage to a channel of said at least one program inhibited memory cell and passing pre-charge voltage to a buffering memory cell located on said source side of said at least one program inhibited memory cell to provide a pre-charge voltage to a channel of said buffering memory cell;

turning off said gating memory cell that is located on said drain side of said program inhibited memory cell; and

applying a program voltage to said word line wherein a channel voltage of said program inhibited memory cell is raised above a level raised by said pre-charge voltage; and

storing said program voltage in said memory cell to be programmed.

18. The method of claim 17 wherein said turning off said gating memory cell is done by lowering the voltage applied to the gate of said gating memory cell.

19. The method of claim 17 wherein said turning off said gating memory cell is done without lowering the voltage applied to the gate of said gating memory cell.

20. The method of claim 17 further comprising applying a predetermined voltage to the gate of said buffering memory cell located adjacent to said program inhibited memory cell on the source side of said program inhibited memory cell.