IP Library Granted Patent US 7,871,896
Granted Patent B2
US 7,871,896 · App. 12/134,087 · Granted Jan 18, 2011

Precision trench formation through oxide region formation for a semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,871,896
App. No.
12/134,087
Granted
Jan 18, 2011
Kind
B2
Abstract

Structures and methods for precision trench formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate, and oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing to the semiconductor substrate, where the first oxygen-containing region is converted to a first oxide region. The method further comprises forming a groove in the semiconductor substrate by eliminating the first oxide region, where the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.

Claims (17)

1. A method for manufacturing a semiconductor device, comprising:

forming a first oxygen-containing region in a semiconductor substrate by performing an oxygen ion implantation to a portion of the semiconductor substrate;

oxidizing the first oxygen-containing region using oxygen contained therein by performing a thermal processing of the semiconductor substrate, wherein the first oxygen-containing region is converted to a first oxide region while suppressing oxidation of a surface of the semiconductor substrate; and

forming a groove in the semiconductor substrate by eliminating the first oxide region, wherein the performing thermal processing comprises subjecting the first oxygen-containing region to a gas low on oxygen.

2. The method for manufacturing the semiconductor device according to claim 1 , wherein the gas low on oxygen comprises an inert gas.

3. The method for manufacturing the semiconductor device according to claim 1 , wherein the forming the first oxide-region comprises:

forming an oxide film on the semiconductor substrate;

forming a photoresist having an opening on the oxide film; and

implanting oxygen ions to the portion of the semiconductor substrate using the photoresist as a mask.

4. The method for manufacturing the semiconductor device according to claim 1 , wherein the oxygen ion implantation to the portion of the semiconductor substrate is performed multiple times at different energy levels with different doses of oxygen ions.

5. The method for manufacturing the semiconductor device according to claim 4 , wherein the oxygen ion implantation is performed using a dose of 3.0×10 17 oxygen ions/cm 2 at implantation energy of 200 KeV, a dose of 2.5×10 17 oxygen ions/cm 2 at implantation energy of 120 KeV, and a dose of 2.5×10 17 ions/cm 2 at implantation energy of 40 KeV.

6. The method for manufacturing the semiconductor device according to claim 5 , wherein the oxygen-containing region has an approximately 0.6 micrometers deep U-like shape.

7. The method for manufacturing the semiconductor device according to claim 1 , wherein the thermal processing is performed for one hour using argon gas at 1200 degrees Celsius.

8. The method for manufacturing the semiconductor device according to claim 1 , wherein the eliminating the first oxide region is performed using a wet etching process.

9. The method for manufacturing the semiconductor device according to claim 8 , wherein the wet etching process is performed using a hydrofluoric acid.

10. The method for manufacturing the semiconductor device according to claim 1 , wherein the oxygen-containing region has an approximately 0.17 micrometers deep U-like shape after the oxygen ion implantation is performed using a dose of 2.5×10 7 ions/cm 2 at implantation energy of 30 KeV.

11. The method for manufacturing the semiconductor device according to claim 1 , wherein the depth of the oxygen-containing region is determined by the energy for the oxygen ion implantation.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2008
From: INOUE, FUMIHIKO; MARUYAMA, TAKAYUKI; WATANABE, TOMOHIRO
To: SPANSION LLC
Reel/Frame 021309/0605 →