IP Library Granted Patent US 7,846,829
Granted Patent B2
US 7,846,829 · App. 12/196,210 · Granted Dec 7, 2010

Stacked solder balls for integrated circuit device packaging and assembly

Assignee: Spansion LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,846,829
App. No.
12/196,210
Granted
Dec 7, 2010
Kind
B2
Abstract

A semiconductor device is provided that includes a semiconductor chip, a plurality of solder bumps that electrically couple the semiconductor chip to the outside, and a metal bump being provided on the surface of each first solder bump which is at least a part of the plurality of solder bumps and being made of a metal having a melting point higher than that of the first solder bump. The wettability of the first solder bump is improved as each metal bump serves as a core when the corresponding first solder bump melts. Thus, the connection reliability of the first solder bump can be improved.

Claims (17)

1. A semiconductor device comprising:

a semiconductor chip;

a plurality of solder bumps that electrically couple the semiconductor chip to an external circuit; and

a metal bump disposed on a surface of a first solder bump of the plurality of solder bumps wherein a width of the metal bump is less than the diameter of the first solder bump and comprising a metal having a melting point higher than that of the first solder bump wherein the first solder bump is positioned between the semiconductor chip and the metal bump.

2. The semiconductor device according to claim 1 , wherein the plurality of solder bumps include a second solder bump that has no metal bump on a surface thereof.

3. The semiconductor device according to claim 1 , wherein the metal bump is stacked on the surface of at least a part of the first solder bump.

4. The semiconductor device according to claim 1 , wherein the metal bump is stacked on a surface of a third solder bump.

5. The semiconductor device according to claim 1 , wherein the metal bump comprises a gold stud bump.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a metal bump on a surface of a first solder bump of a plurality of solder bumps that electrically couple a semiconductor chip to an external electrode wherein the metal bump has a width that is less than the diameter of the first solder bump, the metal bump being made of a metal having a melting point higher than that of the first solder bump; and

bonding the first solder bump on a mounting portion wherein the first solder bump is positioned between the semiconductor chip and the metal bump.

7. The method for manufacturing a semiconductor device according to claim 6 , wherein the step of forming the metal bump on the surface of each first solder bump includes the step of: stacking a metal bump on a surface of a third solder bump on a surface of a fourth solder bump so that metal bumps, the number of which corresponds to surface irregularities of the mounting portion on which the solder bumps are mounted, are formed on the surfaces of the third solder bump and the fourth solder bump.

8. The method for manufacturing a semiconductor device according to claim 6 , wherein the step of forming a metal bump on the surface of each first solder bump includes forming, on the surface of each first solder bump, bumps having different heights corresponding to surface irregularities of the mounting portion on which the solder bumps are mounted.

9. A method for manufacturing a semiconductor device, the method comprising the steps of:

applying, to a surface of a solder bump that electrically couples a semiconductor chip to an external electrode, a flux containing a metal with a higher melting point than that of the solder bump wherein the width of the flux is less than the diameter of the solder bump; and

bonding the solder bump having the surface to which the flux is applied on a mounting portion wherein the solder bump is positioned between the semiconductor chip and the metal.

10. The method for manufacturing a semiconductor device according to any one of claims 6 to 9 , wherein the mounting portion is an interposer on which the semiconductor chip is mounted.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2008
From: TANAKA, JUNJI; HARAYAMA, MASAHIKO; ONODERA, MASANORI
To: SPANSION LLC
Reel/Frame 021791/0489 →
Priority Claims (1)
JP 2007-215189 · Aug 21, 2007 · national
Continuity (1)
Related Publication 20090212423A1 · Aug 27, 2009