IP Library Granted Patent US 8,725,485
Granted Patent B2
US 8,725,485 · App. 12/037,297 · Granted May 13, 2014

Simulation method and simulation apparatus

Inventors: Masato Tatsuoka (Kawasaki, JP); Atsushi Ike (Kawasaki, JP)
Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,725,485
App. No.
12/037,297
Granted
May 13, 2014
Kind
B2
Abstract

A simulation method and apparatus including a restore point setting unit setting restore points in core models for executing threads using parallel processing. The method also includes storing information for reproducing a state the core models at the restore points.

Claims (32)

1. A simulation method comprising:

setting restore points in each of a plurality of core models for executing threads using parallel processing, the restore points being set according to an interval defined by a restore point value which corresponds to a predetermined number of execution operations or simulator cycles, wherein the restore points for each of the plurality of core models, are set simultaneously; and

storing, in a storage unit, when a program counter value is the same as the restore point value information for reproducing a state of each of the plurality of core models at the restore points, wherein after storing the information at a new one of the restore points, the storage unit overwrites previously stored information with information corresponding to the new restore point,

wherein, when a fetched instruction is a break instruction, the restore point is set in one of the plurality of core models and a flag that is referable by the plurality of core models is set,

wherein, when the fetched instruction is not the break instruction and the flag has been set, the restore point is set in the one of the plurality of core models,

wherein, when the fetched instruction is not the break instruction and the flag has not been set, the restore point is not set in the one of the plurality of core models.

2. The simulation method of claim 1 , wherein

the restore points are set periodically and, in each period, simultaneously in the plurality of core models.

3. The simulation method of claim 1 , wherein

after storing the information at a predetermined number of the restore points, the storage unit sequentially overwrites previously stored information with information corresponding to the new restore points.

4. The simulation method of claim 1 , wherein

when one of the restore points has been set part-way through execution of an instruction in any one of the plurality of core models, corresponding restore points are set in other core models of the plurality of core models.

5. The simulation method of claim 1 , wherein the flag is initialized by at least one of an initial setting, a software, a graphical user interface and a break instruction.

6. The simulation method of claim 4 , wherein

the restore points are set at time points freely-selected by a user.

7. The simulation method of claim 1 , wherein

the restore points are set simultaneously in the plurality of core models at a time point freely-selected by a user.

8. The simulation method of claim 1 , wherein

the information is compressed before being stored in the storage unit.

9. The simulation method of claim 1 , wherein

the plurality of core models are simulation models for processors in a multiprocessor, for processor cores in a multicore processor, or master devices in a multi-master/slave device.

10. The simulation method of claim 1 , wherein

each piece of the stored information is managed by being corresponded with a core number of a core model and a program counter value for a timing at which the restore point was set.

11. A simulation device comprising:

a restore point setting configured to set restore points in each of a plurality of core models for executing threads using parallel processing, the restore points being set according to an interval defined by a restore point value which corresponds to a predetermined number of execution operations or simulator cycles, wherein the restore points for each of the plurality of core models are set simultaneously; and

a storage unit configured to store, when a program counter value is the same as the restore point value, information to reproduce a state of each of the plurality of core models at the restore points, wherein after storing the information at one of the restore points, the storage unit overwrites previously stored information with information corresponding to the new restore point,

wherein, when a fetched instruction is a break instruction, the restore point is set in one of the plurality of core models and a flag that is referable by the plurality of core models is set,

wherein, when the fetched instruction is not the break instruction and the flag has been set, the restore point is set in the one of the plurality of core models,

wherein, when the fetched instruction is not the break instruction and the flag has not been set, the restore point is not set in the one of the plurality of core models.

12. The simulation method of claim 1 , further comprising:

judging whether a program counter value is the same as a periodic restore point value, and when the two values are judged to be the same, the information for reproducing a state of each of the plurality of core models is stored.

13. The simulation device of claim 11 , wherein the flag is initialized by at least one of an initial setting, a software, a graphical user interface and the break instruction.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 22, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 044949/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 044938/0360 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2008
From: TATSUOKA, MASATO; IKE, ATSUSHI
To: FUJITSU LIMITED
Reel/Frame 020589/0780 →
Priority Claims (1)
JP 2007-45577 · Feb 26, 2007 · national
Continuity (1)
Related Publication 20080208555A1 · Aug 28, 2008