Cycle simulation method, cycle simulator, and computer product
View Patent ↗It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution block. If the addresses coincide with each other, it is determined whether a cycle of a second execution block currently executing precedes that of the first execution block. If the cycle of the second execution block precedes that of the first executing block, a memory model is accessed. A necessary number of cycles for execution of a j-th instruction is added to the current number of cycles, and the address, a cycle, data, and a data size at the time of the current access (before re-writing) are written in a delay table.
1. A method of simulating a plurality of execution blocks in a large scale integration model in parallel, the method comprising:
simulating a first and a second execution block in parallel;
detecting, when a first instruction is executed by the first block that is selected from among the execution blocks, a number of cycles at a time of completion of the first instruction;
judging whether a second instruction currently being executed by the second block that is selected subsequent to the first block is an instruction to access a memory model;
determining, based on a result of judgment at the judging, whether a first address at which the first block has accessed the memory model coincides with a second address of the memory model, the second address included in the second instruction for the second block to access;
comparing, when the first address coincides with the second address at the determining, a current number of cycles of the second block and the number of cycles detected at the detecting; and
storing, based on a result of comparison at the comparing, the second address and data that has been stored at the second address, in a storage area different from the memory model.
2. The method including according to claim 1 :
detecting, when the second instruction is executed, a number of cycles at a completion of the second instruction;
judging whether a third instruction currently being executed by the first block that is selected again subsequent to the second block is an instruction to access the memory model;
determining whether the second address coincides with a third address of the memory model, the third address included in the third instruction for the first block to access, based on a result of judgment at the judging whether the third instruction is to access the memory model;
comparing a current number of cycles of the first block and the number of cycles detected at the detecting at the end of completion of the second instruction, based on a result of determination at the determining whether the second address coincides with the third address; and
accessing stored address and stored data, based on a result of comparison at the comparing the current number of cycles of the first block and the number of cycles detected at the detecting at the end of completion of the second instruction.
3. A computer-readable recording medium that stores therein a computer program for realizing a method of simulating a plurality of execution blocks in a large scale integration model in parallel, the computer program making a computer execute:
simulating a first and a second execution block in parallel;
detecting, when a first instruction is executed by the first block that is selected from among the execution blocks, a number of cycles at a time of completion of the first instruction;
judging whether a second instruction currently being executed by the second block that is selected subsequent to the first block is an instruction to access a memory model;
determining, based on a result of judgment at the judging, whether a first address at which the first block has accessed the memory model coincides with a second address of the memory model, the second address included in the second instruction for the second block to access;
comparing, when the first address coincides with the second address at the determining, a current number of cycles of the second block and the number of cycles detected at the detecting; and
storing, based on a result of comparison at the comparing, the second address and data that has been stored at the second address, in a storage area different from the memory model.
4. The computer-readable recording medium according to claim 3 , wherein the computer program further makes the computer execute:
detecting, when the second instruction is executed, a number of cycles at a completion of the second instruction;
judging whether a third instruction currently being executed by the first block that is selected again subsequent to the second block is an instruction to access the memory model;
determining whether the second address coincides with a third address of the memory model, the third address included in the third instruction for the first block to access, based on a result of judgment at the judging whether the third instruction is to access the memory model;
comparing a current number of cycles of the first block and the number of cycles detected at the detecting at the end of completion of the second instruction, based on a result of determination at the determining whether the second address coincides with the third address; and
accessing stored address and stored data, based on a result of comparison at the comparing the current number of cycles of the first block and the number of cycles detected at the detecting at the end of completion of the second instruction.
5. A cycle simulator including a processor for simulating a plurality of execution blocks in a large scale integration model in parallel, the cycle simulator comprising:
a detecting unit configured to detect, when a first instruction is executed by a first block that is selected from among the execution blocks, a number of cycles at a time of completion of the first instruction;
a judging unit configured to judge whether a second instruction currently being executed by a second block that is selected subsequent to the first block is an instruction to access a memory model;
a determining unit configured to determine, based on a result of judgment by the judging unit, whether a first address at which the first block has accessed the memory model coincides with a second address of the memory model, the second address included in the second instruction for the second block to access;
a comparing unit configured to compare, when the first address coincides with the second address at the determining, a current number of cycles of the second block and the number of cycles detected by the detecting unit; and
a repository configured to store, based on a result of comparison at the comparing, the second address and data that has been stored at the second address, in a storage area different from the memory model.