Patent Assignment
Reel/Frame 036043/0013
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-07-01
Received: 2015-07-01
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(50)
METHOD AND ARCHITECTURE FOR FAST FLASH MEMORY PROGRAMMING
App. No. 12/405,947
→
DIE OFFSET DIE TO DIE BONDING
App. No. 12/316,042
→
SEMICONDUCTOR DEVICE AND ITS CONTROL METHOD
App. No. 12/283,721
→
MEMORY DEVICE WITH A SELECTION ELEMENT AND A CONTROL LINE IN A SUBSTANTIALLY SIMILAR LAYER
App. No. 12/141,180
→
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
App. No. 12/130,537
→
ENHANCED ERASING OPERATION FOR NON-VOLATILE MEMORY
App. No. 12/129,530
→
MULTIPLE PROGRAMMING OF SPARE MEMORY REGION FOR NONVOLATILE MEMORY
App. No. 12/126,686
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DC-DC CONVERTER, POWER SUPPLY SYSTEM, AND POWER SUPPLY METHOD
App. No. 12/057,001
→
DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
App. No. 12/054,081
→
VOLTAGE BOOSTER BY ISOLATION AND DELAYED SEQUENTIAL DISCHARGE
App. No. 12/014,454
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REDUCED STATE QUADBIT
App. No. 11/958,557
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PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
App. No. 11/956,032
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SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
App. No. 11/953,689
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HIGH RELIABLE AND LOW POWER STATIC RANDOM ACCESS MEMORY
App. No. 11/942,526
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MEMORY CELL ARRAY WITH LOW RESISTANCE COMMON SOURCE AND HIGH CURRENT DRIVABILITY
App. No. 11/983,864
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CONTROL CIRCUIT OF CURRENT MODE DC-DC CONVERTER AND CONTROL METHOD OF CURRENT MODE DC-DC CONVERTER
App. No. 11/936,933
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ERASE, PROGRAMMING AND LEAKAGE CHARACTERISTICS OF A RESISTIVE MEMORY DEVICE
App. No. 11/980,116
→
SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK
App. No. 11/924,823
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POWER SUPPLY CIRCUIT, POWER SUPPLY CONTROL CIRCUIT, AND POWER SUPPLY CONTROL METHOD
App. No. 11/976,507
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METHOD AND CIRCUIT FOR CONTROLLING DC-DC CONVERTER
App. No. 11/898,690
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METHOD AND STRUCTURE OF MINIMIZING MOLD BLEEDING ON A SUBSTRATE SURFACE OF A SEMICONDUCTOR PACKAGE
App. No. 11/895,901
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CAPACITOR STRUCTURE USED FOR FLASH MEMORY
App. No. 11/838,483
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VARIABLE SALICIDE BLOCK FOR RESISTANCE EQUALIZATION IN AN ARRAY
App. No. 11/748,215
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SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE
App. No. 11/746,122
→
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 11/796,582
→
NON-VOLATILE RESISTANCE CHANGING FOR ADVANCED MEMORY APPLICATIONS
App. No. 11/724,788
→
METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS
App. No. 11/615,365
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FLOATING GATE PROCESS METHODOLOGY
App. No. 11/614,767
→
COPPER PROCESS METHODOLOGY
App. No. 11/614,770
→
METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
App. No. 11/612,992
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STRAPPING CONTACT FOR CHARGE PROTECTION
App. No. 11/612,265
→
METHODS AND SYSTEMS FOR MEMORY DEVICES
App. No. 11/639,935
→
METHOD TO PROVIDE A HIGHER REFERENCE VOLTAGE AT A LOWER POWER SUPPLY IN FLASH MEMORY DEVICES
App. No. 11/634,776
→
SEMICONDUCTOR DEVICE, FABRICATION METHOD THEREFOR, AND FILM FABRICATION METHOD
App. No. 11/540,034
→
DC-DC CONVERTER CONTROL CIRCUIT, DC-DC CONVERTER, POWER SUPPLY UNIT, AND DC-DC CONVERTER CONTROL METHOD
App. No. 11/526,051
→
STORAGE DEVICE AND CONTROL METHOD OF STORAGE DEVICE
App. No. 11/510,077
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PLL CIRCUIT AND SEMICONDUCTOR DEVICE
App. No. 11/505,446
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VOLTAGE BOOSTING DEVICE AND METHOD FOR SEMICONDUCTOR DEVICE
App. No. 11/493,467
→
POWER SOURCE CONTROL CIRCUIT, POWER SUPPLY DEVICE, AND CONTROL METHOD FOR THE SAME
App. No. 11/446,140
→
CYCLE SIMULATION METHOD, CYCLE SIMULATOR, AND COMPUTER PRODUCT
App. No. 11/439,124
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MEMORY CELL ARRAY WITH LOW RESISTANCE COMMON SOURCE AND HIGH CURRENT DRIVABILITY
App. No. 11/412,574
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ENHANCED PROCESSOR ELEMENT STRUCTURE IN A RECONFIGURABLE INTEGRATED CIRCUIT DEVICE
App. No. 11/390,131
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STACKED TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING STACKED TYPE SEMICONDUCTOR DEVICE
App. No. 11/339,352
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NOISE FILTER AND FILTERING METHOD
App. No. 11/305,088
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SEMICONDUCTOR MEMORY AND METHOD OF FABRICATING THE SAME
App. No. 11/291,342
→
READ MODE FOR FLASH MEMORY
App. No. 11/189,923
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COMMUNICATION SYSTEM
App. No. 11/131,322
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METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
App. No. 11/075,999
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MULTIPLE DUAL BIT MEMORY INTEGRATED CIRCUIT SYSTEM
App. No. 11/059,139
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CHARGE CONTROL THAT KEEPS CONSTANT INPUT VOLTAGE SUPPLIED TO BATTERY PACK
App. No. 10/954,754
→