Methods and systems for memory devices
View Patent ↗One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell. Other methods and systems are also disclosed.
1. A method for accessing a flash memory cell, comprising:
erasing at least one bit of the memory cell while applying a first channel voltage to a p-well of the memory cell; and
after erasing the at least one bit of the memory cell, performing a soft program operation by applying a second channel voltage to the p-well while concurrently applying a wordline voltage to a wordline coupled to the at least one memory cell, where the second channel voltage is less than the first channel voltage and where the wordline voltage is greater than the first channel voltage.
2. The method of claim 1 , wherein erasing the at least one bit comprises:
injecting a number of charged carriers into a charge trapping dielectric layer of the memory cell to adjust a threshold voltage of the memory cell.
3. The method of claim 2 , wherein performing a soft program operation comprises:
adjusting the threshold voltage of the memory cell by biasing the memory cell to adjust the number of charged carriers in the charge trapping dielectric layer.
4. The method of claim 3 , wherein the memory cell is a flash memory cell.
5. The method of claim 3 , wherein the memory cell is a flash memory cell that is configured to store at least two bits of data.
6. A method for accessing a flash memory cell having a channel region disposed between a source and a drain, and a wordline disposed over the channel region, the method comprising:
erasing a bit of the flash memory cell by applying a voltage of approximately zero volts to the channel region while concurrently applying a first negative wordline voltage to the wordline; and
improving the reliability of data stored in the flash memory cell by applying a second positive wordline voltage to the wordline while concurrently applying a second negative channel voltage to the channel region.
7. The method of claim 6 , wherein improving the reliability of the data further comprises at least one of:
applying a negative source voltage to the source; or
applying a negative drain voltage to the drain.
8. The method of claim 7 , further comprising:
applying a positive voltage to a deep-well that electrically isolates the channel region from a substrate on which the flash memory cell is formed.
9. The method of claim 6 , further comprising:
programming the bit of the flash memory cell by applying a third positive wordline voltage to the wordline while concurrently applying a source-drain voltage between the source and drain.
10. The method of claim 9 , further comprising:
applying a positive voltage to a deep-well that electrically isolates the channel region from a substrate on which the flash memory cell is formed.
11. A method for accessing a memory cell having a channel region disposed between a source and a drain, and a wordline disposed over the channel region, the method comprising:
programming a bit of the memory cell by applying a first channel voltage of approximately zero volts to the channel region while concurrently applying a first positive wordline voltage to the wordline;
erasing the bit of the memory cell by applying the first channel voltage to the channel region while concurrently applying a first negative wordline voltage to the wordline;
improving the reliability of data stored in the memory cell by applying a second positive wordline voltage to the wordline while concurrently applying a second channel voltage less than the first channel voltage to the channel region.
12. The method of claim 6 , further comprising:
applying a positive voltage to a deep-well that electrically isolates the channel region from a substrate on which the flash memory cell is formed.