Enhanced erasing operation for non-volatile memory
View Patent ↗Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
1. A semiconductor device comprising:
a memory cell array having a plurality of non-volatile memory cells;
a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array; and
a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage, wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage.
2. The semiconductor device according to claim 1 , further comprising a regulator circuit that maintains the negative voltage applied to the word line at or below the predetermined voltage.
3. The semiconductor device according to claim 2 , further comprising a comparator that performs a comparison between the negative voltage and a reference voltage and forwards an operating signal based on the comparison, wherein the regulator circuit maintains the negative voltage at or below the predetermined voltage based on the operating signal.
4. The semiconductor device according to claim 3 , wherein the applying the positive voltage to the well is initiated when the operating signal is received by the positive voltage generating circuit.
5. The semiconductor device according to claim 3 , wherein the predetermined voltage is the reference voltage.
6. The semiconductor device according to claim 1 , further comprising a well voltage applying circuit coupled to the positive voltage generating circuit for applying the positive voltage to the well.
7. The semiconductor device according to claim 1 , wherein the applying the positive voltage is performed after the applying the negative voltage by a threshold time.
8. The semiconductor device according to claim 7 , wherein the threshold time enables the negative voltage to reach the predetermined value by delaying a capacitive coupling between the word line and the well by the threshold time since the applying of the negative voltage.
9. A method for controlling a semiconductor device, comprising:
applying a negative voltage to a word line of a memory cell array during an erasing operation of the memory cell array having a plurality of non-volatile memory cells; and
applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage,
wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage.
10. The method according to claim 9 , wherein the applying the positive voltage is performed a duration after the applying the negative voltage.
11. The method according to claim 10 , wherein the duration enables the negative voltage to reach the predetermined voltage.
12. The method according to claim 9 , the applying the positive voltage to the well of the memory cell when the negative voltage reaches the predetermined value suppress a capacitive coupling of the word line and the well until the negative voltage reaches the predetermined value.
13. The method of according to claim 9 , wherein the negative voltage is maintained at the predetermined voltage when the negative voltage reaches the predetermined voltage.
14. A system for suppressing a capacitive coupling of a word line and a well associated with a memory cell array in a nonvolatile memory device, comprising:
a negative voltage generating circuit for applying a negative voltage to the word line during an erasing operation of the memory cell array; and
a positive voltage generating circuit for applying a positive voltage to the well when the negative voltage reaches a predetermined voltage,
wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage.
15. The system according to claim 14 , further comprising a regulator circuit that maintains the negative voltage applied to the word line at or below the predetermined voltage.
16. The system according to claim 15 , further comprising a comparator that performs a comparison between the negative voltage and a reference voltage and forwards an operating signal based on the comparison, wherein the regulator circuit maintains the negative voltage at or below the predetermined voltage based on the operating signal.
17. The system according to claim 16 , wherein the applying the positive voltage to the well is initiated when the operating signal is received by the positive voltage generating circuit.
18. The system according to claim 14 , further comprising a well voltage applying circuit coupled to the positive voltage generating circuit for applying the positive voltage to the well.
19. The system according to claim 14 , wherein the applying the positive voltage is performed after the applying the negative voltage by a threshold time.
20. The system according to claim 19 , wherein the threshold time enables the negative voltage to reach the predetermined value by delaying a capacitive coupling between the word line and the well by the threshold time since the applying of the negative voltage.