Method and architecture for fast flash memory programming
View Patent ↗Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.
1. A method of reading an array of flash memory cells, wherein said array comprises a plurality of sectors of said memory cells, wherein a sector comprises a plurality of units of said memory cells, wherein a unit comprises a plurality of columns, wherein a column comprises cells, wherein a cell comprises a bit, said method comprising:
reading first data from a first sector of units, wherein said first data comprises a first bit in a first column page from a first unit in said first sector;
outputting said first data to a bit line driver;
repeating said reading and outputting for second data from said first sector, wherein said second data comprises a second bit in said first column page from said first unit in said first sector;
repeating said reading and said outputting of data until said first sector is read.
2. The method recited in claim 1 further comprising repeating said reading and said outputting data for a second sector of units.
3. The method recited in claim 2 further comprising repeating said reading and outputting strings for sectors until said array is read.
4. The method of claim 1 wherein said unit comprises 8 bits.
5. The method of claim 4 wherein said first data comprises:
a first bit of a first page of a first unit in said first sector;
a first bit of a first page of a second unit in said first sector;
a first bit of a first page of a third unit in said first sector;
a first bit of a first page of a fourth unit in said first sector;
a first bit of a first page of a fifth unit in said first sector;
a first bit of a first page of a sixth unit in said first sector;
a first bit of a first page of a seventh unit in said first sector; and
a first bit of a first page of an eighth unit in said first sector.
6. The method of claim 1 wherein said unit comprises 16 bits.
7. The method of claim 1 wherein a flash memory cell comprises a control gate accessed by a word line, a drain region accessed by a first bit line, source region accessed by a second bit line, and a channel region, wherein a method of reading said memory cell is read according to the following:
applying a first voltage to said word line;
applying a second voltage to said first bit line;
grounding said second bit line, wherein said applying said first and second voltages and said grounding said second bit line are concurrent; and
measuring a current through said channel, wherein if said measured current is greater than a reference current, said cell reads as programmed, and wherein if said measured current is less than said reference current, said cell reads as erased.
8. The method of claim 1 wherein said first voltage is 3V˜5V, and said second voltage is 1V˜2V.
9. The method of claim 1 wherein said array further comprises a sector select component, wherein said sector select component determines a sector to be read.