Variable salicide block for resistance equalization in an array
View Patent ↗The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.
1. A method of fabricating at least a portion of a memory array comprising:
forming a charge trapping dielectric layer;
forming a plurality of bitlines, the plurality of bitlines configured to operate as acting sources and acting drains;
forming a plurality of wordlines electrically coupled to a common discharge node, wherein the charge trapping dielectric layer is dis nosed between one or more of the plurality of bitlines and one or more of the plurality of wordlines; and
processing the plurality of wordlines to substantially equalize a resistance between each of the wordlines and the common discharge node.
2. The method of claim 1 , wherein equalizing the resistance between each of the wordlines and the common discharge node comprises:
determining a calculated resistance between respective wordlines and the common discharge node, wherein the calculated resistance is a function of an amount of desired charge dissipation into the common discharge node; and
forming a salicide blocking material disposed between respective wordlines and the common discharge node, the salicide blocking material configured to provide the equalized resistance based upon the calculated resistance.
3. The method of claim 1 , wherein equalizing the resistance between each of the wordlines and the common discharge node comprises:
depositing a layer of salicide blocking material on the plurality of word lines;
masking at least a portion of the salicide blocking material;
selectively etching the unmasked portion of the salicide blocking material to form an exposed region over a portion of the plurality of wordlines; and
forming a salicide on the exposed region of the plurality of the wordlines.
4. The method of claim 3 , wherein processing the plurality of wordlines comprises:
patterning the salicide blocking material to selectively vary the resistance between each word line and the common discharge node for resistance equalization of each respective wordline.
5. The method of claim 3 , wherein the salicide blocking material is patterned into a triangular wedge shape extending across the plurality of wordlines and oriented to block salicide formation along each respective wordline for a length inversely proportional to a distance from the common discharge element, thereby selectively equalizing the resistance between each wordline and the common discharge node.
6. The method of claim 1 , wherein the common discharge node comprises at least one capacitor electrode of a capacitor element.
7. The method of claim 1 , wherein the resistance of each respective word line to the common discharge node is at least about 1 Mega-Ohm.
8. The method of claim 6 , wherein the capacitor element comprises a metal-oxide-semiconductor (MOS) capacitor formed by a method comprising:
forming a conductive well in a semiconductor substrate, wherein the conductive well comprises a first capacitor electrode;
forming an insulating layer disposed above at least a portion of the conductive well; and
forming a conductive layer disposed above the insulating layer, wherein the conductive layer comprises a second capacitor electrode.
9. The method of claim 8 , wherein the conductive layer comprises silicon dioxide.
10. The method of claim 1 , wherein the charge trapping layer comprises a gate oxide material.
11. A method of fabricating at least a portion of a memory array comprising:
calculating a desired resistance as a function of an amount of desired charge dissipation into at least one charge dissipating region;
forming a charge trapping dielectric layer on a semiconductor substrate;
performing a bitline implant to form a plurality of bitlines in the semiconductor substrate, wherein the plurality of bitlines are configured to operate as acting sources and acting drains for dual bit operation;
depositing a conductive material over the charge trapping dielectric layer;
selectively patterning the deposited conductive material to form a plurality of wordlines that are each respectively connected to a common shorting element coupled to the at least one charge dissipating region; and
forming at least one salicide blocking layer configured to selectively form salicided interfaces on a portion of the respective wordlines, the salicided interfaces providing a resistance between each respective word line and the common shorting element based on the calculated desired resistance.
12. The method of claim 11 ,
wherein the salicided interfaces of each wordline have different surface areas, thereby substantially equalizing the resistance between the plurality of wordlines and the at least one common charge dissipating region.
13. The method of claim 11 , further comprising:
forming a top salicide blocking layer extending across a top subset of the plurality of wordlines, the top salicide blocking layer configured to block salicide formation along respective word lines in the top subset for a length inversely proportional to a distance from a first common discharge element, thereby selectively equalizing the resistance between each wordline in the top subset and the first common discharge element; and
forming a bottom salicide blocking layer extending across bottom subset of the plurality of wordlines, the bottom salicide blocking layer configured to block salicide formation along respective wordlines in the bottom subset for a length inversely proportional to a distance from a second common discharge element, thereby selectively equalizing the resistance between each word line in the bottom subset and the second common discharge element.
14. The method of claim 13 , wherein
the top and bottom salicide blocking layers are configured into a bow-tie formation.
15. The method of claim 12 , wherein forming at least one salicide blocking layer comprises:
depositing a salicide blocking material over the plurality of wordlines;
masking a portion of the salicide blocking material;
selectively patterning the salicide blocking material to form an exposed region over a portion of the plurality of wordlines; and
forming a salicide blocking layer on the exposed region of the plurality of wordlines.
16. The method of claim 12 , wherein the resistance between each respective wordline and the common charge dissipating region is at least about 1 Mega-Ohm.