Granted Patent B2

US 7,706,183 · App. 11/189,923 · Granted Apr 27, 2010

Abstract

Claims (29)

1. A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, comprising:

receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command;

identifying a starting address for a page including the received address, the page including multiple rows of memory cells in the array of memory cells;

setting the address register to the starting address for the page;

determining whether all memory cells in a selected row in the page are in a non-programmed state;

determining whether the received read command indicates that the read command is a partial page read command when it is determined that all memory cells in the selected row in the page are in a non-programmed state; and

outputting data indicative of a non-programmed state of the selected row in the page when it is determined that the read command is a partial page read command.

2. The method of claim 1 , comprising:

determining whether all rows in the page have been read when it is determined that the read command indicates a fUll page read command; and

outputting data corresponding to data stored within the page to an output memory.

3. The method of claim 2 , comprising:

incrementing the address to a next row in the page when it is determined that all rows in the page have not been read; and

repeating the determining whether all memory cells in the row are in a non-programmed state.

4. The method of claim 1 , where the memory cells include SON 0 S (semiconductor-oxide-nitride-semiconductor) type NOR memory cells.

5. The method of claim 1 , where the page includes four rows of memory cells.

6. The method of claim 1 , further comprising:

configuring a dynamic reference bit associated with a selected row of memory cells in the page to indicate whether all memory cells in the selected row are in a non-programmed state.

7. The method of claim 6 , where the dynamic reference bit is stored in memory cell located in a spare area associated with the memory array.

8. The method of claim 1 , where the memory cells include a dual-bit charge storage element configured to include at least two charge.

9. A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, comprising:

receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command;

identifying a starting address for a page including the received address, wherein the page includes multiple rows of memory cells in the array of memory cells;

setting the address register to the starting address for the page;

determining whether all memory cells in a selected row of the page are in a non-programmed state;

performing a read operation on the selected row when it is determined that all memory cells in the selected row are not in a non-programmed state;

determining whether all memory cells in the selected row have been read;

repeating performing a read operation for the un-read memory cells in the selected row;

determining whether the received read command indicates that the read command is a partial page read command when it is determined that all memory cells in the selected row are in a non-programmed state; and

outputting data indicative of the non-programmed state of the selected row if it is determined that the read command indicates a partial page read command.

Assignments (8)