Semiconductor memory and method of fabricating the same
View Patent ↗A semiconductor memory includes first and second source regions that are formed in a semiconductor substrate and run in orthogonal directions. The first and second source regions are diffused regions and are electrically connected to each other at crossing portions thereof. The semiconductor device may further include drain regions formed in the semiconductor substrate, bit lines that run in the direction in which the second source region runs, and a source line formed above the second source region, wherein a contact between the source line and the second source region is aligned with contacts between the bit lines and drain regions formed in the semiconductor substrate.
1. A semiconductor memory comprising:
a semiconductor substrate having drain regions and first source regions, each of the drain regions and first source regions comprising a diffused region formed in the semiconductor substrate and having a width, the drain regions and first source regions running in a first direction orthogonal to the width thereof, the semiconductor substrate further having at least one second source region formed therein, wherein the at least one second source region has a length that runs in a second direction orthogonal to the first direction, wherein the length of the at least one second source region is substantially longer than the width of the first source regions;
bit lines running in the second direction and coupled to the drain regions in the semiconductor substrate by a plurality of bit line contacts; and
a source metal wiring line formed above each of the at least one second source region, wherein one or more source contacts are formed to connect the source metal wiring line and the at least one second source region therebelow, and wherein each of the one or more source contacts is aligned in the first direction with one or more corresponding ones of the bit line contacts such that each of the one or more source contacts is in line in the first direction with the one or more corresponding ones of the bit line contacts.
2. The semiconductor memory as claimed in claim 1 , wherein the first source regions and the at least one second source region are diffused regions and are electrically connected to each other at crossing portions thereof.
3. The semiconductor memory as claimed in claim 1 , wherein the first source regions and the at least one second source region comprise straight-line regions.
4. The semiconductor memory as claimed in claim 1 , wherein the bit lines are arranged at both sides of the at least one second source region.
5. The semiconductor memory as claimed in claim 1 , wherein a distance between the source metal wiring line and one of the bit lines adjacent thereto is greater than a distance between adjacent ones of the bit lines.
6. The semiconductor memory as claimed in claim 1 , further comprising word lines running in the first direction, wherein the first source regions run between adjacent word lines, and wherein each of the one or more source contacts and the one or more corresponding ones of the bit line contacts are aligned in the first direction between adjacent word lines such that each of the one or more source contacts is in line in the first direction with the one or more corresponding ones of the bit line contacts.
7. The semiconductor memory as claimed in claim 6 , wherein the word lines include gate electrodes formed above channels in the semiconductor substrate defined by adjacent ones of the drain regions and the first source regions formed in the semiconductor substrate.
8. The semiconductor memory as claimed in claim 1 , wherein the semiconductor memory is a NOR type flash memory having floating gates.
9. A method of fabricating a semiconductor device comprising the steps of:
forming a first source region in a semiconductor substrate having a width, the first source region having a length running in a first direction orthogonal to the width thereof;
forming a second source region in the semiconductor substrate, the second source region having a length thereof running in a second direction orthogonal to the first direction;
forming a first metal wiring line above the second source region and running in the second direction parallel to and above the second source region; and
forming a second metal wiring line as a bit line formed above the semiconductor substrate and running in the second direction, wherein the second metal wiring line is parallel to and adjacent to the first metal wiring line.
10. The method as claimed in claim 9 , further comprising a step of forming floating gates and gate electrodes prior to forming the second source region.
11. The method as claimed in claim 9 , further comprising a step of forming a floating gate and a gate electrode after the second source region is formed.
12. The method as claimed in claim 9 , further comprising the steps of:
forming a bit line contact connecting the bit line to a drain region formed in the semiconductor substrate; and
forming a source line contact connecting the first metal wiring line to the second source region, wherein the source line contact is formed in alignment in the first direction with the bit line contact.