High reliable and low power static random access memory
View Patent ↗Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.
1. A system that facilitates access of data associated with a memory, comprising:
an optimized buffer component comprising a plurality of buffer cells that can store data to facilitate access of data associated with the memory; and
at least one precharge component that can generate a single precharge control signal that establishes a respective precharged state on two or more data access lines within the optimized buffer component to facilitate access of one or more buffer cells of the plurality of buffer cells.
2. The system of claim 1 , the at least one precharge component is communicatively coupled to at least one of the data access lines selectively associated with at least one buffer cell of the plurality of buffer cells.
3. The system of claim 1 , the optimized buffer component further comprises:
at least one buffer cell address decoder, wherein the at least one precharge component is further communicatively coupled to at least one signal conductor path through the at least one buffer cell address decoder and generates at least one precharged state thereon.
4. The system of claim 3 , the at least one buffer cell address decoder is a tree-type decoder.
5. The system of claim 4 , the optimized buffer component further comprises:
at least one input/output sensor component, wherein the at least one precharge component is further communicatively coupled to at least one signal conductor path of the at least one input/output sensor component and generates at least one precharged state thereon.
6. The system of claim 1 , wherein a data access line associated with the optimized buffer component is precharged to facilitate reducing errors associated with parasitic electronic effects during an operation associated with the optimized buffer component, the operation comprising at least one of a read, a write, a refresh, an update, or an erase, or a combination thereof.
7. The system of claim 1 , further comprising a memory component that is associated with the optimized buffer component, wherein the optimized buffer component facilitates the execution of operations associated with the memory component.
8. The system of claim 7 , the memory component is at least one a nonvolatile memory or a volatile memory.
9. The system of claim 1 , further comprising:
a just-in-time power component that provides an enabling signal to at least one wordline associated with at least one buffer cell of the plurality of buffer cells in response to part upon at least one of an address signal, a write enable signal, or a read enable signal, or a combination thereof, received by the just-in-time power component in order to facilitate reducing power consumption associated with an operation associated with the at least one buffer cell.
10. The system of claim 9 , the enabling signal is provided for a period of time, the period of time is based on the amount of time required for access of the at least one buffer cell in order to perform an operation.
11. The system of claim 10 , the enabling signal is determined according to a logic equation: WORDLINE=!{ADDRESS NAND (![WRITE_ENABLE NOR READ_ENABLE])}, wherein WORDLINE is the enable signal, ADDRESS is the address signal, WRITE_ENABLE is the write enable signal, and READ_ENABLE is the read enable signal.
12. An electronic device comprising at least a portion of the system of claim 1 .
13. The electronic device of claim 12 , wherein the electronic device comprises at least one of a computer, a laptop computer, network equipment, a media player, a media recorder, a television, a smart card, a phone, a cellular phone, a smart phone, an electronic organizer, a personal digital assistant, a portable email reader, a digital camera, an electronic game, an electronic device associated with digital rights management, a Personal Computer Memory Card International Association (PCMCIA) card, a trusted platform module (TPM), a Hardware Security Module (HSM), set-top boxes, a digital video recorder, a gaming console, a navigation system, a secure memory device with computational capabilities, a device with at least one tamper-resistant chip, an electronic device associated with industrial control systems, or an embedded computer in a machine, or a combination thereof, wherein the machine comprises one of an airplane, a copier, a motor vehicle, or a microwave oven.
14. The system of claim 1 wherein the precharge component can receive an externally generated precharge control signal and apply the signal to establish a respective a precharged state on two or more data access lines within the optimized buffer component to facilitate access of one or more buffer cells of the plurality of buffer cells.
15. The system of claim 14 the precharge component receives precharge control signals from at least one of an external precharge control signal generator, another optimized buffer component, or other precharge components of the system.
16. The system of claim 5 , the single precharge control signal substantially simultaneously establishes a different precharged state on at least one of a bitline of the buffer component, the tree-type decoder component, or at least one input/output sensor component.
17. The system of claim 4 the single precharge control signal substantially simultaneously establishes a different precharged state on one or more nodes associated with the tree-type decoder component.
18. A system that facilitates access of data associated with a memory, comprising:
an optimized buffer component comprising a plurality of buffer cells that can store data to facilitate access of data associated with the memory; and
a just-in-time power component that provides an enabling signal to at least one wordline associated with at least one buffer cell of the plurality of buffer cells in response to at least one of an address signal, a write enable signal, or a read enable signal, or a combination thereof, received by the just-in-time power component in order to facilitate reducing power consumption associated with an operation associated with the at least one buffer cell.
19. The system of claim 18 , the enabling signal is provided for a period of time, the period of time is based on the an amount of time required for access of the at least one buffer cell in order to perform an operation.
20. The system of claim 19 , the enabling signal is determined according to a logic equation: WORDLTNE=!{ADDRESS NAND (![WRITE_ENABLE NOR READ_ENABLE])}, wherein WORDLINE is the enabling signal, ADDRESS is the address signal, WRITE_ENABLE is the write enable signal, and READ_ENABLE is the read enable signal.