Capacitor structure used for flash memory
A method of forming a capacitor for use as a charge pump with flash memory, comprising: (a) concurrently forming polysilicon gates on a semiconductor body in a core region and a polysilicon middle capacitor plate in a peripheral region, (b) forming a first dielectric layer over the polysilicon gates and the middle capacitor plate, (c) planarizing the first dielectric layer to expose a top portion of the polysilicon gates and a top portion of the middle capacitor plate, (d) forming a second dielectric layer over the top portion of the middle capacitor layer, (e) concurrently forming patterning a second polysilicon layer in the core region and a third capacitor plate in the periphery region and (f) connecting the third capacitor plate to the source/drain well.
1. A method of forming a capacitor for use as a charge pump with flash memory, comprising:
forming a first polysilicon layer over a semiconductor body;
patterning the first polysilicon layer into a polysilicon gate disposed over a core region of the semiconductor body and a first polysilicon capacitor plate disposed over a peripheral region of the semiconductor body;
forming a first dielectric layer over the polysilicon gate and the first polysilicon capacitor plate;
planarizing the first dielectric layer to expose a top portion of the polysilicon gate and a top portion of the first polysilicon capacitor plate;
forming a second dielectric layer over the top portion of the first polysilicon capacitor plate;
forming a second polysilicon layer over the top portion of the polysilicon gate and over the second dielectric layer;
patterning a portion of the second polysilicon layer over the second dielectric layer to form a second capacitor plate in the periphery region; and
electrically connecting the second capacitor plate to the semiconductor body.
2. The method of claim 1 , wherein the first dielectric layer comprises: a gate oxide, silicon, silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide.
3. The method of claim 1 , wherein the second dielectric layer comprises: gate oxide, silicon, silicon dioxide, silicon nitride, silicon oxynitride, and aluminum oxide.
4. The method of claim 1 , where the first polysilicon capacitor plate and the second capacitor plate form a capacitor that is configured to deliver a pulse for a program or erase operation.
5. A method of forming a capacitor for use in flash memory, comprising:
forming a first dielectric layer over a core region and a peripheral region of a semiconductor body;
forming a first polysilicon layer over the first dielectric layer;
patterning the first polysilicon layer to form a gate over the core region and a first capacitor plate over the periphery region;
forming source/drain regions in the core region about opposing sides of the gate;
forming a second dielectric layer over both the gate and the first capacitor plate;
planarizing the second dielectric layer to expose a top portion of the gate and a top portion of the first capacitor plate;
forming a third dielectric layer over the top portion of the first capacitor layer;
forming and patterning a second polysilicon layer extending over the gate and over the third dielectric layer; and
electrically connecting the second polysilicon layer over the third dielectric layer to the semiconductor body.