IP Library › Assignment 041175/0939
Patent Assignment
Reel/Frame 041175/0939

RELEASE OF SECURITY INTEREST

Recorded: 2016-12-22 Received: 2016-12-22 Pages: 13
Assignor
Assignees
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
SPANSION LLC
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications (61)
Wireless Locating and Monitoring System
App. No. 14/864,401
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 14/136,977
→
SONOS FLASH MEMORY DEVICE
App. No. 13/275,989
→
WIRELESS LOCATING AND MONITORING SYSTEM
App. No. 13/245,739
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING
App. No. 13/216,142
→
ADAPTING AUDIO SIGNALS TO A CHANGE IN DEVICE ORIENTATION
App. No. 13/213,430
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 13/094,668
→
PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD
App. No. 13/022,517
→
SEMICONDUCTOR DEVICE AND METHOD TO MANUFACTURE THEREOF
App. No. 12/837,323
→
MEMORY SYSTEM AND METHOD
App. No. 12/819,794
→
WIRELESS LOCATING AND MONITORING SYSTEM
App. No. 12/815,377
→
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 12/788,177
→
METHOD AND APPARATUS FOR DYNAMICALLY DETECTING ENVIRONMENTAL CONDITIONS AND ADJUSTING DRIVE STRENGTH IN RESPONSE TO THE DETECTING
App. No. 12/509,249
→
METHOD FOR MITIGATING IMPRINT IN A FERROELECTRIC MEMORY
App. No. 12/415,918
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING
App. No. 12/341,879
→
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
App. No. 12/332,146
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/256,333
→
LINEAR DROP-OUT REGULATOR CIRCUIT
App. No. 12/255,356
→
MEMORY SYSTEM AND METHOD
App. No. 12/239,532
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 12/239,566
→
MANUFACTURING STACKED SEMICONDUCTOR DEVICE
App. No. 12/210,113
→
METHOD FOR MANUFACTURING SONOS FLASH MEMORY
App. No. 12/193,266
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/217,096
→
SEMICONDUCTOR MANUFACTURING EQUIPMENT AND MANUFACTURING METHOD OF THE SAME
App. No. 12/026,425
→
Method of operating a processing chamber used in forming electronic devices
App. No. 11/950,339
→
2T/2C FERROELECTRIC RANDOM ACCESS MEMORY WITH COMPLEMENTARY BIT-LINE LOADS
App. No. 11/875,922
→
CAPACITOR STRUCTURE USED FOR FLASH MEMORY
App. No. 11/838,483
→
METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH
App. No. 11/741,998
→
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 11/796,582
→
LOW POWER BETA MULTIPLIER START-UP CIRCUIT AND METHOD
App. No. 11/653,533
→
WIRELESS LOCATING AND MONITORING SYSTEM
App. No. 11/567,144
→
Non-volatile memory on resonant tunneling devices
App. No. 11/595,426
→
REFERENCE VOLTAGE CIRCUIT
App. No. 11/523,122
→
STORAGE DEVICE AND CONTROL METHOD THEREFOR
App. No. 11/443,770
→
MULTI MEDIA CARD WITH HIGH STORAGE CAPACITY
App. No. 11/400,902
→
INDEPENDENT CONTROL OF CORE SYSTEM BLOCKS FOR POWER OPTIMIZATION
App. No. 11/343,841
→
FREQUENCY MODULATOR, CIRCUIT, AND METHOD THAT USES MULTIPLE VECTOR ACCUMULATION TO ACHIEVE FRACTIONAL-N FREQUENCY SYNTHESIS
App. No. 11/172,691
→
PAGE BUFFER ARCHITECTURE FOR PROGRAMMING, ERASING AND READING NANOSCALE RESISTIVE MEMORY DEVICES
App. No. 11/139,227
→
SKATE BOOT
App. No. 11/117,413
→
SPORTING BOOT
App. No. 11/057,766
→
PARTIALLY DE-COUPLED CORE AND PERIPHERY GATE MODULE PROCESS
App. No. 10/619,797
→
FERROELECTRIC NON-VOLATILE LOGIC ELEMENTS
App. No. 10/613,427
→
STRUCTURE AND METHOD FOR PREVENTING PROCESS-INDUCED UV RADIATION DAMAGE IN A MEMORY CELL
App. No. 10/460,282
→
STABILITY ROBUSTNESS USING A NON-INTEGER ORDER FILTER IN A CIRCUIT
App. No. 10/335,457
→
METHOD FOR CONFIGURING CHIP SELECTS IN MEMORIES
App. No. 10/327,221
→
SWITCHED CAPACITOR FILTER
App. No. 10/325,398
→
DIGITAL CONFIGURABLE MACRO ARCHITECTURE
App. No. 10/272,231
→
ORGANIC SPIN-ON ANTI-REFLECTIVE COATING OVER INORGANIC ANTI-REFLECTIVE COATING
App. No. 10/262,221
→
FERROELECTRIC RANDOM ACCESS MEMORY CONFIGURABLE OUTPUT DRIVER CIRCUIT
App. No. 10/233,276
→
SYSTEM AND METHOD OF ACQUIRING DELAY, SETUP AND HOLD VALUES FOR INTEGRATED CIRCUIT CELLS
App. No. 10/229,527
→
METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
App. No. 10/190,351
→
METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
App. No. 10/190,350
→
SERVO CONTROLLER AND SERVO CONTROL METHOD
App. No. 10/187,944
→
METHOD OF DRIVING A SEMICONDUCTOR MEMORY
App. No. 10/160,050
→
FERROELECTRIC NON-VOLATILE LOGIC ELEMENTS
App. No. 10/076,058
→
FERROELECTRIC RANDOM ACCESS MEMORY CONFIGURABLE OUTPUT DRIVER CIRCUIT
App. No. 09/950,560
→
NON-VOLATILE SEMICONDUCTOR MEMORY AND ITS DRIVING METHOD
App. No. 09/927,387
→
DIGITAL CONFIGURABLE MACRO ARCHITECTURE
App. No. 09/909,045
→
CAPACITIVELY COUPLED FERROELECTRIC RANDOM ACCESS MEMORY CELL AND A METHOD FOR MANUFACTURING THE SAME
App. No. 09/873,772
→
METHOD FOR MANUFACTURING A FERROELECTRIC MEMORY CELL INCLUDING CO-ANNEALING
App. No. 09/816,425
→
SERVO CONTROLLER AND SERVO CONTROL METHOD
App. No. 09/782,297
→