IP Library Granted Patent US 7,786,587
Granted Patent B2
US 7,786,587 · App. 12/217,096 · Granted Aug 31, 2010

Semiconductor device and method for manufacturing thereof

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Quick Facts
Patent No.
US 7,786,587
App. No.
12/217,096
Granted
Aug 31, 2010
Kind
B2
Abstract

A semiconductor device 100 includes a semiconductor substrate 14 , a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20 , and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20 . The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12 , and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Claims (36)

1. A semiconductor device comprising:

a semiconductor substrate;

a connection electrode disposed on an upper surface of the semiconductor substrate and connected to an integrated circuit on the semiconductor substrate;

a through electrode which penetrates the semiconductor substrate and the connection electrode; and

an insulation portion interposed between the semiconductor substrate and the through electrode, wherein

the through electrode is integrally formed to protrude outward from upper surfaces of the semiconductor substrate and the connection electrode, and connected to the connection electrode in a region where the through electrode penetrates the connection electrode.

2. The semiconductor device according to claim 1 , wherein:

the semiconductor substrate includes a first through hole which penetrates the semiconductor substrate, and a second through hole which vertically penetrates the insulation portion inside the first through hole;

the insulation portion is disposed inside the first through hole; and

the through electrode is disposed inside the second through hole.

3. The semiconductor device according to claim 2 , wherein:

the first through hole is tapered in a direction from the upper surface to a lower surface of the semiconductor substrate;

the insulation portion is formed to fill the first through hole; and

the second through hole is tapered from the lower surface to the upper surface of the semiconductor substrate.

4. The semiconductor device according to claim 1 , further comprising at least one of a first bonding bump formed on an upper surface of the through electrode and a second bonding bump formed on a lower surface of the through electrode.

5. A method for manufacturing a semiconductor device comprising:

bonding a first support member formed of a support base material and a support adhesive agent on an upper surface of a semiconductor substrate provided with a connection electrode by directing the support adhesive agent downward;

forming a first through hole which penetrates the semiconductor substrate;

forming an insulation portion inside the first through hole;

forming a second through hole which vertically penetrates the insulation portion and the connection electrode, and further penetrates the support adhesive agent inside the first through hole; and

integrally forming a through electrode in a region corresponding to the semiconductor substrate, the connection electrode and the support adhesive agent inside the second through hole.

6. The method for manufacturing the semiconductor device according to claim 5 , wherein:

the first support member is provided with a stopper layer interposed between the support base material and the support adhesive agent; and

forming the second through hole includes forming the second through hole which penetrates the insulation portion, the connection electrode and the support adhesive agent from a lower surface of the semiconductor substrate to reach the stopper layer.

7. The method for manufacturing the semiconductor device according to claim 5 , further comprising forming a first bonding bump in a region corresponding to the support adhesive agent inside the second through hole.

8. The method for manufacturing the semiconductor device according to claim 5 , further comprising:

bonding a second support member to a lower surface of the semiconductor substrate; and

forming a second bonding bump to a lower surface of the through electrode using the second support member as a mask after eliminating the support adhesive agent and the support base material, wherein:

forming the second through hole includes forming the second through hole which penetrates the second support member, the insulation portion, the connection electrode, and the support adhesive agent inside the first through hole; and

forming the through electrode includes forming the through electrode using the second support member as the mask.

9. The method for manufacturing the semiconductor device according to claim 5 , wherein:

forming the first through hole includes eliminating the semiconductor substrate in a direction from an upper surface to a lower surface thereof; and

forming the second through hole includes eliminating the insulation portion, the connection electrode and the support adhesive agent in the direction from the lower surface to the upper surface of the semiconductor substrate.

10. A semiconductor device wherein:

a plurality of the semiconductor devices according to claim 1 are stacked; and

vertically stacked semiconductor devices among the plurality of the semiconductor devices are connected with each other via the through electrode.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 22, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 041175/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040908/0960 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036042/0212 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2008
From: HOSHINO, MASATAKA; FUKUYAMA, RYOTO; TAYA, KOJI
To: SPANSION LLC
Reel/Frame 021540/0111 →