Patent Assignment
Reel/Frame 040908/0960
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2016-12-14
Received: 2016-12-14
Pages: 14
Assignor
CYPRESS SEMICONDUCTOR CORPORATION
Executed: 2016-09-28
Assignee
MONTEREY RESEARCH, LLC
3945 FREEDOM CIRCLE, SUITE 900, SANTA CLARA, CA, 95054, UNITED STATES
Covered Applications
(61)
Wireless Locating and Monitoring System
App. No. 14/864,401
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 14/136,977
→
SONOS FLASH MEMORY DEVICE
App. No. 13/275,989
→
WIRELESS LOCATING AND MONITORING SYSTEM
App. No. 13/245,739
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING
App. No. 13/216,142
→
ADAPTING AUDIO SIGNALS TO A CHANGE IN DEVICE ORIENTATION
App. No. 13/213,430
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 13/094,668
→
PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD
App. No. 13/022,517
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BEVERAGE MAKER
App. No. 29/369,100
→
CUP SHAPED CONTAINER
App. No. 29/367,460
→
SEMICONDUCTOR DEVICE AND METHOD TO MANUFACTURE THEREOF
App. No. 12/837,323
→
MEMORY SYSTEM AND METHOD
App. No. 12/819,794
→
WIRELESS LOCATING AND MONITORING SYSTEM
App. No. 12/815,377
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SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 12/788,177
→
METHOD AND APPARATUS FOR DYNAMICALLY DETECTING ENVIRONMENTAL CONDITIONS AND ADJUSTING DRIVE STRENGTH IN RESPONSE TO THE DETECTING
App. No. 12/509,249
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METHOD FOR MITIGATING IMPRINT IN A FERROELECTRIC MEMORY
App. No. 12/415,918
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING
App. No. 12/341,879
→
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
App. No. 12/332,146
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/256,333
→
LINEAR DROP-OUT REGULATOR CIRCUIT
App. No. 12/255,356
→
MEMORY SYSTEM AND METHOD
App. No. 12/239,532
→
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
App. No. 12/239,566
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MANUFACTURING STACKED SEMICONDUCTOR DEVICE
App. No. 12/210,113
→
METHOD FOR MANUFACTURING SONOS FLASH MEMORY
App. No. 12/193,266
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/217,096
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SEMICONDUCTOR MANUFACTURING EQUIPMENT AND MANUFACTURING METHOD OF THE SAME
App. No. 12/026,425
→
Method of operating a processing chamber used in forming electronic devices
App. No. 11/950,339
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2T/2C FERROELECTRIC RANDOM ACCESS MEMORY WITH COMPLEMENTARY BIT-LINE LOADS
App. No. 11/875,922
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CAPACITOR STRUCTURE USED FOR FLASH MEMORY
App. No. 11/838,483
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METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH
App. No. 11/741,998
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SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
App. No. 11/796,582
→
LOW POWER BETA MULTIPLIER START-UP CIRCUIT AND METHOD
App. No. 11/653,533
→
WIRELESS LOCATING AND MONITORING SYSTEM
App. No. 11/567,144
→
Non-volatile memory on resonant tunneling devices
App. No. 11/595,426
→
REFERENCE VOLTAGE CIRCUIT
App. No. 11/523,122
→
STORAGE DEVICE AND CONTROL METHOD THEREFOR
App. No. 11/443,770
→
MULTI MEDIA CARD WITH HIGH STORAGE CAPACITY
App. No. 11/400,902
→
INDEPENDENT CONTROL OF CORE SYSTEM BLOCKS FOR POWER OPTIMIZATION
App. No. 11/343,841
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FREQUENCY MODULATOR, CIRCUIT, AND METHOD THAT USES MULTIPLE VECTOR ACCUMULATION TO ACHIEVE FRACTIONAL-N FREQUENCY SYNTHESIS
App. No. 11/172,691
→
PAGE BUFFER ARCHITECTURE FOR PROGRAMMING, ERASING AND READING NANOSCALE RESISTIVE MEMORY DEVICES
App. No. 11/139,227
→
PARTIALLY DE-COUPLED CORE AND PERIPHERY GATE MODULE PROCESS
App. No. 10/619,797
→
FERROELECTRIC NON-VOLATILE LOGIC ELEMENTS
App. No. 10/613,427
→
STRUCTURE AND METHOD FOR PREVENTING PROCESS-INDUCED UV RADIATION DAMAGE IN A MEMORY CELL
App. No. 10/460,282
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STABILITY ROBUSTNESS USING A NON-INTEGER ORDER FILTER IN A CIRCUIT
App. No. 10/335,457
→
METHOD FOR CONFIGURING CHIP SELECTS IN MEMORIES
App. No. 10/327,221
→
SWITCHED CAPACITOR FILTER
App. No. 10/325,398
→
DIGITAL CONFIGURABLE MACRO ARCHITECTURE
App. No. 10/272,231
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ORGANIC SPIN-ON ANTI-REFLECTIVE COATING OVER INORGANIC ANTI-REFLECTIVE COATING
App. No. 10/262,221
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FERROELECTRIC RANDOM ACCESS MEMORY CONFIGURABLE OUTPUT DRIVER CIRCUIT
App. No. 10/233,276
→
SYSTEM AND METHOD OF ACQUIRING DELAY, SETUP AND HOLD VALUES FOR INTEGRATED CIRCUIT CELLS
App. No. 10/229,527
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METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
App. No. 10/190,351
→
METHOD FOR PRODUCING CRYSTALLOGRAPHICALLY TEXTURED ELECTRODES FOR TEXTURED PZT CAPACITORS
App. No. 10/190,350
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SERVO CONTROLLER AND SERVO CONTROL METHOD
App. No. 10/187,944
→
METHOD OF DRIVING A SEMICONDUCTOR MEMORY
App. No. 10/160,050
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FERROELECTRIC NON-VOLATILE LOGIC ELEMENTS
App. No. 10/076,058
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FERROELECTRIC RANDOM ACCESS MEMORY CONFIGURABLE OUTPUT DRIVER CIRCUIT
App. No. 09/950,560
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NON-VOLATILE SEMICONDUCTOR MEMORY AND ITS DRIVING METHOD
App. No. 09/927,387
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DIGITAL CONFIGURABLE MACRO ARCHITECTURE
App. No. 09/909,045
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CAPACITIVELY COUPLED FERROELECTRIC RANDOM ACCESS MEMORY CELL AND A METHOD FOR MANUFACTURING THE SAME
App. No. 09/873,772
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METHOD FOR MANUFACTURING A FERROELECTRIC MEMORY CELL INCLUDING CO-ANNEALING
App. No. 09/816,425
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SERVO CONTROLLER AND SERVO CONTROL METHOD
App. No. 09/782,297
→