IP Library Granted Patent US 6,856,181
Granted Patent B1
US 6,856,181 · App. 10/335,457 · Granted Feb 15, 2005

Stability robustness using a non-integer order filter in a circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,856,181
App. No.
10/335,457
Granted
Feb 15, 2005
Kind
B1
Abstract

A non-integer order controller for providing stability in a circuit. The non-integer order controller may be in either a feed-forward path or a feedback path of the circuit. Thus, the non-integer order controller is operable to provide stability for the circuit. The closed loop system may be a phase lock loop.

Claims (27)

1. A device for providing stability in a circuit comprising:

a non-integer order controller in one of a feed-forward path and a feedback path of said circuit, wherein said non-integer order controller is operable to provide stability for said circuit.

2. The device of claim 1 , wherein said non-integer order controller is in said feed-forward path.

3. The device of claim 1 , wherein said non-integer order controller is in said feedback path.

4. The device of claim 1 , wherein said circuit is a phase lock loop.

5. The device of claim 4 , wherein poles and zeroes of said non-integer order controller each have a respective pre-determined value to minimize a settling time of said phase lock loop.

6. The device of claim 1 , wherein said non-integer order controller comprises circuit elements configured in a recursive pattern.

7. The device of claim 1 , wherein said non-integer order controller is implemented with computer software.

8. A method of providing stability to a system, comprising:

a) receiving a signal in a closed loop system;

b) modifying said signal with a non-integer order function to provide stability to said system; and

c) passing said signal along in said closed loop system.

9. The method of claim 8 , wherein said system comprises a phase lock loop.

10. The method of claim 8 , wherein said b) comprises modifying said signal using software.

11. The method of claim 8 , wherein said b) comprises modifying said signal using hardware.

12. The method of claim 8 , wherein said a) comprises receiving said signal from a feed-forward path of said closed loop system.

13. The method of claim 8 , wherein said a) comprises receiving said signal from a feedback path of said closed loop system.

14. A phase lock loop circuit comprising:

a feed-forward path;

a feedback path coupled to said feed-forward path; and

a non-integer order controller in one of said feed-forward path and said feedback path and operable to provide stability.

15. The phase lock loop circuit of claim 14 , wherein said non-integer order controller comprises circuit elements in a recursive pattern.

16. The phase lock loop circuit of claim 15 , wherein said circuit elements comprise resistors and capacitors.

17. The phase lock loop circuit of claim 14 , wherein said non-integer order controller is further operable as a low pass filter.

18. The phase lock loop circuit of claim 14 , wherein poles and zeroes of said non-integer order controller have pre-determined values to minimize a settling time of said phase lock loop.

19. The phase lock loop circuit of claim 14 , wherein said non-integer order controller comprises poles and zeroes that are operable to simulate a single pole/single zero filter of order m, wherein m is a non-integer and wherein m is a pre-determined value operable to improve a figure of merit of said phase lock loop.

20. The phase lock loop circuit of claim 19 , wherein said value of m is operable to reduce a locking time of said phase lock loop as compared to an integer order controller.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 22, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 041175/0939 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040908/0960 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2002
From: YAHIAOUI, YOUCEF
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 013638/0570 →